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부품번호 | BR24L04F-W 기능 |
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기능 | 5128 bit electrically erasable PROM | ||
제조업체 | ROHM Semiconductor | ||
로고 | |||
전체 25 페이지수
Memory ICs
BR24L04-W / BR24L04F-W / BR24L04FJ-W
BR24L04FV-W / BR24L04FVM-W
512×8 bit electrically erasable PROM
BR24L04-W / BR24L04F-W / BR24L04FJ-W /
BR24L04FV-W / BR24L04FVM-W
The BR24L04-W series is 2-wire (I2C BUS type) serial EEPROMs which are electrically programmable.
∗ I2C BUS is a registered trademark of Philips.
zApplications
General purpose
zFeatures
1) 512 registers × 8 bits serial architecture.
2) Single power supply (1.8V to 5.5V).
3) Two wire serial interface.
4) Self-timed write cycle with automatic erase.
5) 16byte Page Write mode.
6) Low power consumption.
Write (5V) : 1.2mA (Typ.)
Read (5V) : 0.2mA (Typ.)
Standby (5V) : 0.1µA (Typ.)
7) DATA security
Write protect feature (WP pin).
Inhibit to WRITE at low VCC.
8) Small package - - - DIP8 / SOP8 / SOP-J8 / SSOP-B8 / MSOP-8
9) High reliability EEPROM with Double-Cell structure
10) High reliability fine pattern CMOS technology.
11) Endurance : 1,000,000 erase / write cycles
12) Data retention : 40 years
13) Filtered inputs in SCL•SDA for noise suppression.
14) Initial data FFh in all address.
zAbsolute maximum ratings (Ta=25°C)
Parameter
Symbol
Limits
Supply voltage
VCC −0.3 to +6.5
800(DIP8) ∗1
450(SOP8) ∗2
Power dissipation
Pd 450(SOP-J8) ∗2
300(SSOP-B8) ∗3
310(MSOP8) ∗4
Storage temperature
Tstg
−65 to +125
Operating temperature
Topr
−40 to +85
Terminal voltage
− −0.3 to VCC+0.3
∗1 Reduced by 8.0mW for each increase in Ta of 1°C over 25°C.
∗2 Reduced by 4.5mW for each increase in Ta of 1°C over 25°C.
∗3 Reduced by 3.0mW for each increase in Ta of 1°C over 25°C.
∗4 Reduced by 3.1mW for each increase in Ta of 1°C over 25°C.
Unit
V
mW
°C
°C
V
1/25
Memory ICs
zBlock diagram
BR24L04-W / BR24L04F-W / BR24L04FJ-W
BR24L04FV-W / BR24L04FVM-W
A0 1
A1 2
A2 3
GND 4
4kbit EEPROM array
9bit
Address
decoder
9bits
Slave word
address register
8bit
Data
register
START
Control logic
High voltage generator
STOP
ACK
Vcc level detect
8 VCC
7 WP
6 SCL
5 SDA
zPin configuration
Fig.2 BLOCK DIAGRAM
VCC WP SCL SDA
8765
BR24L04-W
BR24L04F-W
BR24L04FJ-W
BR24L04FV-W
BR24L04FVM-W
1234
A0 A1 A2 GND
Fig.3 PIN LAYOUT
zPin name
Pin name
VCC
GND
A0
A1, A2
SCL
SDA
WP
I/O
−
−
−
IN
IN
IN / OUT
IN
Function
Power supply
Ground (0V)
Out of use
Slave address set
Serial clock input
Slave and word address,
serial data input, serial data output
Write protect input
∗1 An open drain output requires a pull-up resistor.
∗1
4/25
4페이지 Memory ICs
zWP timing
SCL
BR24L04-W / BR24L04F-W / BR24L04FJ-W
BR24L04FV-W / BR24L04FVM-W
SDA
DATA (1)
D1 D0
ACK
WP
DATA (n)
ACK
STOP BIT
tWR
tSU : WP
Fig.6(a) WP TIMING OF THE WRITE OPERATION
tHD : WP
SCL
SDA
DATA (1)
D1 D0
ACK
WP
DATA (n)
tHIGH : WP
ACK
Fig.6(b) WP TIMING OF THE WRITE CANCEL OPERATION
•For the WRITE operation, WP must be “LOW” during the period of time from the rising edge of the clock which takes in
D0 of first byte until the end of tWR. ( See Fig.6 (a) )
During this period, WRITE operation is canceled by setting WP “HIGH”. ( See Fig.6 (b) )
•In the case of setting WP “HIGH” during tWR, WRITE operation is stopped in the middle and the data of accessing
address is not guaranteed. Please write correct data again in the case.
7/25
7페이지 | |||
구 성 | 총 25 페이지수 | ||
다운로드 | [ BR24L04F-W.PDF 데이터시트 ] |
당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는 |
구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
BR24L04F-W | 5128 bit electrically erasable PROM | ROHM Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |