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BR93LC46-W 데이터시트 PDF




ROHM Semiconductor에서 제조한 전자 부품 BR93LC46-W은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 BR93LC46-W 자료 제공

부품번호 BR93LC46-W 기능
기능 6416bits serial EEPROM
제조업체 ROHM Semiconductor
로고 ROHM Semiconductor 로고


BR93LC46-W 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




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BR93LC46-W 데이터시트, 핀배열, 회로
Memory ICs
BR93LC46-W / BR93LC46F-W / BR93LC46RF-W /
BR93LC46FJ-W / BR93LC46RFJ-W / BR93LC46FV-W
64×16bits serial EEPROM
BR93LC46-W / BR93LC46F-W / BR93LC46RF-W /
BR93LC46FJ-W / BR93LC46RFJ-W / BR93LC46FV-W
The BR93LC46-W series are CMOS serial input / output-type memory circuits (EEPROMs) that can be programmed
electrically. Each is configured of 64 words × 16 bits (1,024 bits), and each word can be accessed individually and data
read from it and written to it. Operation control is performed using five types of commands.
The commands, addresses, and data are input through the DI pin under the control of the CS and SK pins. In a write
operation, the internal status signal (READY or BUSY) can be output from the DO pin.
zApplications
VCRs, TVs, printers, car stereos, cordless telephones, short wave radios, programmable DIP switches, and
other battery-powered equipment requiring low voltage and low current
zFeatures
1) 64 words × 16 bits EEPROM
2) Operating voltage range
When reading : 2.0 to 5.5V
When writing : 2.7 to 5.5V
3) Low current consumption
Operating (at 5V) : 3mA (Max.)
Standby (at 5V) : 5µA (Max.)
4) Address can be incremented automatically during
read operations.
5) Auto erase and auto complete functions can be used
during write operations.
6) A write instruction inhibit function allows :
- write protection when power supply voltage is low.
- write disable state at power up.
- writing using command codes.
7) Compact packages
8) Display of READY / BUSY status
9) TTL-compatible input / output
10) Rewriting possible up to 100,000 times
11) Data can be stored for ten years without corruption.
zBlock diagram
CS
Command decode
Control
Clock generation
SK
Command
DI
register
DO Dummy bits
Power supply
voltage detector
Write
disable
High voltage
generator
Address
buffer
6bits
Address
decoder
6bits
Data
register
16bits
R/W
amplifier
16bits
1,024bits
EEPROM array




BR93LC46-W pdf, 반도체, 판매, 대치품
Memory ICs
BR93LC46-W / BR93LC46F-W / BR93LC46RF-W /
BR93LC46FJ-W / BR93LC46RFJ-W / BR93LC46FV-W
zMeasurement circuits
VCC
VCC
VCC
GND
IOL
DO
V VOL
VCC
GND
IOH
DO
V VOH
Control output to "LOW"
Fig.3 "LOW" output voltage circuit
Control output to "HIGH"
Fig.4 "HIGH" output voltage circuit
VIN=0~VCC
VCC
VCC
ILI
A CS,SK,DI
GND
VCC
VCC
ILO
CS DO A
GND
VO=0~VCC
Fig.5 Input leak current circuit
Fig.6 Output leak current circuit
fSK=1MHz / 250kHz / 200kHz
VIN=VIH / VIL
WRITE / READ INPUT
CS
SK
DI
VCC
A ICC
VCC
GND
DO
OPEN
Fig.7 Supply current circuit
Vcc
A ISB
CS Vcc
SK DO OPEN
DI GND
Fig.8 Standby current circuit
zCircuit operation
(1) Command mode
With these ICs, commands are not recognized or acted upon until the start bit is received. The start bit is taken as
the first “1” that is received after the CS pin rises.
Command
Read (READ) 1
Start
bit
1
Operating
code
Address
10 A5~A0
Data
Write enabled (WEN)
Write (WRITE) 2
Write all addresses (WRAL) 2
1
1
1
00 11XXXX
01 A5~A0 D15~D0
00 01XXXX D15~D0
Write disabled (WDS)
1
00 00XXXX
Erase (ERASE) 3
1
11 A5~A0
Chip erase (ERAL) 3
1
00 10XXXX
X: Either VIH or VIL
1 After setting of the read command and input of the SK clock, data corresponding to the specified address is output,
with data corresponding to upper addresses then output in se-quence. (Auto increment function)
2 When the write or write all addresses command is executed, all data in the selected memory cell is erased
autematically, and the input data is writen to the cell.
3 These modes are optinal modes. Please contact Rohm for information on operation timing.

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BR93LC46-W 전자부품, 판매, 대치품
Memory ICs
BR93LC46-W / BR93LC46F-W / BR93LC46RF-W /
BR93LC46FJ-W / BR93LC46RFJ-W / BR93LC46FV-W
(5) Write enable (Fig.11)
These ICs are set to the write disabled state by the internal reset circuit when the power is turned on. Therefore,
before performing a write command, the write enable command must be executed. When this command is
executed, it remains valid until a write disable command is issued or the power supply is cut off. However, read
commands can be used in either the write enable or write disable state.
CS
SK
DI 1 0 0 1 1
DO
High Z
Fig.11 Write enable cycle timing
(6) Write (Fig.12)
This command writes the input 16 bits data (D15 to D0) to the specified address (A5 to A0). Actual writing of the data
begins after CS falls (following the 25th clock pulse after the start bit input), and D0 is in the Acquire state.
STATUS is not detected if CS = LOW after the time tE/W. When STATUS is detected (CS = HIGH), no commands are
accepted while DO is LOW (BUSY). Therefore, no commands should be input during this period.
CS
12
SK
4
9 10
tCS STATUS
25
DI
1
DO
High Z
0 1 A5 A4
A1 A0 D15 D14
Fig.12 Write cycle timing (WRITE)
D1 D0
tSV
BUSY READY
tE / W
(STATUS)
After time tCS following the fall of CS, after input of the write command), if CS is set to HIGH, the write execute = BUSY
(LOW) and the command wait status READY (HIGH) are output.
If in the command wait status (STATUS = READY), the next command can be performed within the time tE /W. Thus, if
data is input via SK and DI with CS = HIGH in the tE/W period, erroneous operations may be performed. To avoid this,
make sure that DI = LOW when CS = HIGH. (Caution is especially important when common input ports are used.) This
applies to all of the write commands.

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관련 데이터시트

부품번호상세설명 및 기능제조사
BR93LC46-W

6416bits serial EEPROM

ROHM Semiconductor
ROHM Semiconductor

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