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BR93LC66RF 데이터시트 PDF




ROHM Semiconductor에서 제조한 전자 부품 BR93LC66RF은 전자 산업 및 응용 분야에서
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부품번호 BR93LC66RF 기능
기능 4/096-Bit Serial Electrically Erasable PROM
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BR93LC66RF 데이터시트, 핀배열, 회로
Memory ICs
4,096-Bit Serial Electrically Erasable PROM
BR93LC66 / BR93LC66F / BR93LC66RF / BR93LC66FV
Features
• Low power CMOS Technology
• 256 × 16 bit configuration
• 2.7V to 5.5V operation
• Low power dissipation
– 3mA (max.) active current: 5V
– 5µA (max.) standby current: 5V
• Auto increment for efficient data bump
• Automatic erase-before-write
• Hardware and software write protection
– Default to write-disable state at power up
– Software instructions for write-enable / disable
– Vcc lockout inadvertent write protection
• 8-pin SOP / 8-pin SSOP-B / 8-pin DIP packages
• Device status signal during write cycle
• TTL compatible Input / Output
• 100,000 ERASE / write cycles
• 10 years Data Retention
Pin assignments
CS 1
8 VCC NC 1
8 N.C.
SK 2
DI 3
7 N.C.
BR93LC66 /
BR93LC66RF
6 N.C.
VCC 2
CS 3
BR93LC66F /
BR93LC66FV
7 GND
6 DO
DO 4
5 GND SK 4
5 DI
Pin descriptions
Pin
Name
Function
CS
SK
DI
DO
GND
N.C.
N.C.
VCC
Chip select input
Serial clock input
Start bit, operating code, address, and serial
data input
Serial data output, READY / BUSY internal
status display output
Ground
Not connected
Not connected
Power supply
Overview
The BR93LC66 series are CMOS serial input / output-type memory circuits (EEPROMs) that can be programmed
electrically. Each is configured of 256 words × 16 bits (4096 bits), and each word can be accessed individually and
data read from it and written to it.
Operation control is performed using five types of commands. The commands, addresses, and data are input
through the DI pin under the control of the CS and SK pins. In a write operation, the internal status signal (READY or
BUSY) can be output from the DO pin.
1




BR93LC66RF pdf, 반도체, 판매, 대치품
Memory ICs
BR93LC66 / BR93LC66F / BR93LC66RF / BR93LC66FV
Circuit operation
(1) Command mode
With these ICs, commands are not
recognized or acted upon until the
Command
Start Operating
bit code
Address
Data
start bit is received. The start bit is
Read (READ)1
1 10 A7 ~ A0
taken as the first “1” that is received
after the CS pin rises.
1 After setting of the read command
and input of the SK clock, data corre-
sponding to the specified address is
Write Enabled (WEN)
Write (WRITE)2
Write to All Addresses (WRAL)2
Write Disabled (WDS)
1
1
1
1
00 11XXXXXX
01 A7 ~ A0 D15 ~ D0
00 01XXXXXX D15 ~ D0
00 00XXXXXX
output, with data corresponding to up-
Erase (ERASE)3
1 11 A7 ~ A0
per addresses then output in se-
quence. (Auto increment function)
2 When the write or write all address-
Chip Erase (ERAL)3
X: Either VIH or VIL
1 00 10XXXXXX
es command is executed, all data in the selected memory cell is erased automatically, and the input data is written to
the cell.
3 These modes are optional modes. Please contact Rohm for information on operation timing.
(2) Operation timing characteristics
(unless otherwise noted, Ta = – 40 to 85°C, VCC = 5V ± 10%)
Parameter
Symbol
SK clock frequency
fSK
SK "H" time
tSKH
SK "L" time
tSKL
CS "L" time
tCS
CS setup time
tCSS
DI setup time
tDIS
CS hold time
tCSH
DI hold time
tDIH
Data "1" output delay time
tPD1
Data "0" output delay time
tPD0
Time from CS to output confirmation
tSV
Time from CS to output High impedance tDF
Write cycle time
tE / W
Min.
450
450
450
50
100
0
100
Typ.
Max.
1
500
500
500
100
10
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
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BR93LC66RF 전자부품, 판매, 대치품
Memory ICs
BR93LC66 / BR93LC66F / BR93LC66RF / BR93LC66FV
(4) Reading (Figure 2)
When the read command is acknowledged, the data
(16 bits) for the input address is output serially. The
data is synchronized with the SK rise during A0 acqui-
sition and a “0” (dummy bit) is output. All further data is
output in synchronization with the SK pulse rises.
(5) Write enable (Figure 3)
These ICs are set to the write disabled state by the in-
ternal reset circuit when the power is turned on.
Therefore, before performing a write command, the
write enable command must be executed. When this
command is executed, it remains valid until a write
disable command is issued or the power supply is cut
off. However, read commands can be used in either
the write enable or write disable state.
(6) Write (Figure 4)
This command writes the input 16-bit data (D15 to D0)
to the specified address (A7 to A0). Actual writing of
the data begins after CS falls (following the 27th clock
pulse after the start bit input), and DO is in the Acquire
state.
STATUS is not detected if CS = LOW after the time
tE / W. When STATUS is detected (CS = HIGH), no com-
mands are accepted while DO is LOW (BUSY). There-
fore, no commands should be input during this period.
CS
1
SK
12
4
DI 1 1 0 A7 A6
DO
High-Z
11 12
A1 A0
0 D15 D14
27 28
2
D1 D0 D15 D14
1 If the first data input following the rise of the start bit CS is "1", the start bit is acknowledged. Also, if a "1" is input following several zeroes in succession,
the "1" is recognized as the start bit, and subsequent operation commences. This applies also to all commands described subsequently.
2 Address auto increment function: These ICs are equipped with an address auto increment function which is effective only during reading operations.
With this function, if the SK clock is input following execution of one of the above reading commands, data is read from upper addresses in succession.
CS is held in HIGH state during automatic incrementing.
Fig.2 Read cycle timing (READ)
CS
SK
DI
1
00
11
DO
High-Z
Fig.3 Write enable cycle timing
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부품번호상세설명 및 기능제조사
BR93LC66RF

4/096-Bit Serial Electrically Erasable PROM

ROHM Semiconductor
ROHM Semiconductor

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