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PDF BR93LL46FV Data sheet ( Hoja de datos )

Número de pieza BR93LL46FV
Descripción 1/024-Bit Serial Electrically Erasable PROM
Fabricantes ROHM Semiconductor 
Logotipo ROHM Semiconductor Logotipo



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Memory ICs
1,024-Bit Serial Electrically Erasable PROM
BR93LL46F / BR93LL46FV
Features
• Low power CMOS technology
• 64 × 16 bit configuration
• 1.8V to 4.0V operation
• Low power dissipation
– 0.5mA (typ.) active current
– 0.4µA (typ.) standby current
• Auto increment for efficient data dump
• Automatic erase-before-write
• Hardware and software write protection
– Defaults to write-disabled state at power up
– Software instructions for write-enable / disable
– Vcc lockout inadvertent write protection
• 8-pin SOP / 8-pin SSOP-B packages
• Device status signal during write cycle
• 100,000 ERASE / WRITE cycles
• 10 years Data Retention
Pin assignments
N.C. 1
8 N.C.
VCC 2
7 GND
BR93LL46F
BR93LL46FV
CS 3
6 DO
SK 4
5 DI
(SOP8 / SSOP-B8)
Pin descriptions
Pin Name
Function
N.C.
VCC
CS
SK
DI
DO
GND
N.C.
Not connected
Power supply
Chip select input
Serial clock input
Start bit, operating code, address, and
serial data input
Serial data output, READY / BUSY
internal status display output
Ground
Not connected
Overview
The BR93LC46F and BR93LL46FV are CMOS serial input / output-type memory circuits (EEPROMs) that can be
programmed electrically. Each is configured of 64 words × 16 bits (1,024 bits), and each word can be accessed indi-
vidually and data read from it and written to it. Operation control is performed using five types of commands. The
commands, addresses, and data are input through the DI pin under the control of the CS and SK pins. In a write
operation, the internal status signal (READY or BUSY) can be output from the DO pin.
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BR93LL46FV pdf
Memory ICs
BR93LL46F / BR93LL46FV
(2) Reading
CS
(1)
SK
12
4
DI 1 1 0 A5 A4
DO
High-Z
9 10
A1 A0
0 D15 D14
25 26
(2)
D1 D0 D15 D14
Fig.2 Read cycle timing (READ)
When the read command is acknowledged, the data
(16 bits) for the input address is output serially. The
data is synchronized with the SK rise during A0 acqui-
sition and a “0” (dummy bit) is output. All further data is
output in synchronization with the SK pulse rises.
( 1) Start bit
The start bit is taken as the first “1” that is received
after the CS pin rises. Also, if “0” is input several times
followed by “1”, the “1” is recognized as a start bit, and
subsequent operation commences.
This applies also to the following commands.
( 2) Address auto increment function
These ICs are equipped with an address auto incre-
ment function which is effective only during reading
operations. With this function, if the SK clock is input
following execution of one of the above reading com-
mands, data is read from upper addresses in succes-
sion. CS is held in HIGH state during automatic incre-
menting.
(3) Write enable
CS
SK
DI 1 0 0 1 1
DO High-Z
Fig.3 Cycle timing that allows overwriting
These ICs are set to the write disabled state by the
internal reset circuit when the power is turned on.
Therefore, before performing a write command, the
write enable command must be executed. When this
command is executed, it remains valid until a write dis-
able command is issued or the power supply is cut off.
However, read commands can be used in either the
write enable or write disable state.
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BR93LL46FV arduino
Memory ICs
External dimensions (Units: mm)
BR93LL46F
5.0 ± 0.2
85
14
1.27
0.4 ± 0.1 0.3Min.
SOP8
0.15
BR93LL46F / BR93LL46FV
BR93LL46FV
3.0 ± 0.2
85
14
(0.52) 0.65 0.22 ± 0.1
0.3Min.
SSOP-B8
0.1
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