Datasheet.kr   

BRT1A16G PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 BRT1A16G
기능 Quad Differential Receivers BRF1A/ BRF2A/ BRS2B/ BRR1A/ and BRT1A
제조업체 Agere Systems
로고 Agere Systems 로고 


전체 12 페이지

		

No Preview Available !

BRT1A16G 데이터시트, 핀배열, 회로
Data Sheet
April 2001
Quad Differential Receivers
BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A
Features
s Pin equivalent to the general-trade 26LS32 device,
with improved speed, reduced power consumption,
and significantly lower levels of EMI
s High input impedance approximately 8 k
s Four line receivers per package
s 400 Mbits/s maximum data rate when used with
Agere Systems Inc. data transmission drivers
s Meets enhanced small device interface (ESDI)
standards
s 4.0 ns maximum propagation delay
s <0.20 V input sensitivity
s 1.2 V to +7.2 V common-mode range
s 40 °C to +125 °C ambient operating temperature
range (wider than the 41 Series)
s Single 5.0 V ± 10% supply
s Output defaults to logic 1 when inputs are left
open*
s Available in four package types
s Lower power requirement than the 41 Series
Description
These quad differential receivers accept digital data
over balanced transmission lines. They translate
differential input logic levels to TTL output logic
levels. All devices in this family have four receivers
with a common enable control. These receivers are
pin equivalent to the general-trade 26LS32, but offer
increased speed and decreased power consumption.
They replace the Agere 41 Series receivers.
* This feature is available on BRF1A and BRF2A.
The BRF1A device is the generic receiver in this
family and requires the user to supply external
resistors on the circuit board for impedance
matching.
The BRF2A is identical to the BRF1A, but has an
electrostatic discharge (ESD) protection circuit
added to significantly improve the ESD human-body
model (HBM) characteristics on the differential input
terminals.
The BRS2B is identical to the BRF2A, but has a
preferred state feature that places the output in the
high state when the inputs are open, shorted to
ground, or shorted to the power supply.
The BRR1A is equivalent to the BRF1A, but has a
110 resistor connected across the differential
inputs. This eliminates the need for an external
resistor when terminating a 100 impedance line.
This device is designed to work with the DP1A or
PNPA in point-to-point applications.
The BRT1A is equivalent to the BRF1A; however, it
is provided with a Y-type resistor network across the
differential inputs and terminated to ground. The
Y-type termination provides the best EMI results.
This device is not recommended for applications
where the differences in ground voltage between the
driver and the receiver exceed 1 V. This device is
designed to work with the DG1A or PNGA in point-to-
point applications.
The powerdown loading characteristics of the
receiver input circuit are approximately 8 krelative
to the power supplies; hence, they will not load the
transmission line when the circuit is powered down.
For those circuits with termination resistors, the line
will remain impedance matched when the circuit is
powered down.
The packaging options that are available for these
quad differential line drivers include a 16-pin DIP; a
16-pin, J-lead SOJ; a 16-pin, gull-wing small-outline
integrated circuit (SOIC); and a 16-pin, narrow-body,
gull-wing SOIC.




BRT1A16G pdf, 반도체, 판매, 대치품
Quad Differential Receivers
BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A
Data Sheet
April 2001
Timing Characteristics
Table 4. Timing Characteristics (See Figure 4 and Figure 5.)
For propagation delays (tPLH and tPHL) over the temperature range, see Figure 9 and Figure 10.
Propagation delay test circuit connected to output is shown in Figure 6.
TA = –40 °C to +125 °C, VCC = 5 V ± 0.5 V.
Parameter
Symbol
Min
Typ
Max
Propagation Delay:
Input to Output High
tPLH 1.5 2.5 4.0
Input to Output Low
tPHL 1.5 2.5 4.0
Disable Time, CL = 5 pF:
High-to-high Impedance
tPHZ
5
12
Low-to-high Impedance
tPLZ — 5 12
Pulse Width Distortion, ltpHL tpLHI:
Load Capacitance (CL) = 15 pF
tskew1
0.7
Load Capacitance (CL) = 150 pF
tskew1
4.0
Output Waveform Skews:
Part-to-Part Skew, TA = 75 °C
tskew1p-p
0.8
1.4
Part-to-Part Skew, TA = –40 °C to +125 °C tskew1p-p
— 1.5
Same Part Skew
tskew
0.3
Enable Time:
High Impedance to High
tPZH
8
12
High Impedance to Low
tPZL — 8 12
Rise Time (20%—80%)
ttLH
— 3.0
Fall Time (80%—20%)
ttHL
— 3.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
6
5
4
tPLH (TYP)
3
2
tPHL (TYP)
1
0
0 25 50 75 100 125 150 175 200
LOAD CAPACITANCE, CL (pF)
12-3462(F)
Note: This graph is included as an aid to the system designers. Total circuit delay varies with load capacitance. The total delay is the sum of the
delay due to the external capacitance and the intrinsic delay of the device.
Figure 3. Typical Extrinsic Propagation Delay vs. Load Capacitance at 25 °C
4 Agere Systems Inc.

4페이지










BRT1A16G 전자부품, 판매, 대치품
Data Sheet
April 2001
Quad Differential Receivers
BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A
ESD Failure Models
Agere employs two models for ESD events that can
cause device damage or failure:
1. An HBM that is used by most of the industry for
ESD-susceptibility testing and protection-design
evaluation. ESD voltage thresholds are dependent
on the critical parameters used to define the model.
A standard HBM (resistance = 1500 ,
capacitance = 100 pF) is widely used and, therefore,
can be used for comparison purposes.
2. A charged-device model (CDM), which many
believe is the better simulator of electronics
manufacturing exposure.
Table 5 and Table 6 illustrates the role these two
models play in the overall prevention of ESD damage.
HBM ESD testing is intended to simulate an ESD event
from a charged person. The CDM ESD testing
simulates charging and discharging events that occur in
production equipment and processes, e.g., an
integrated circuit sliding down a shipping tube.
The HBM ESD threshold voltage presented here was
obtained by using the following circuit parameters:
Table 5. Typical ESD Thresholds for Data
Transmission Receivers
Device
HBM Threshold
Differential Others
Inputs
BRF1A, BRR1A,
BRT1A
BRF2A, BRS2B
>800
>2000
>2000
>2000
CDM
Threshold
>1000
>2000
Table 6. ESD Damage Protection
Control
Model
ESD Threat Controls
Personnel
Processes
Wrist straps.
ESD shoes.
Antistatic flooring.
Human body
model (HBM).
Static-dissipative
materials.
Air ionization.
Charged-device
model (CDM).
Latch Up
Latch-up evaluation has been performed on the data transmission receivers. Latch-up testing determines if power-
supply current exceeds the specified maximum due to the application of a stress to the device under test. A device
is considered susceptible to latch up if the power supply current exceeds the maximum level and remains at that
level after the stress is removed.
Agere performs latch up testing per an internal test method that is consistent with JEDEC Standard No. 17
(previously JC-40.2) CMOS Latch Up Standardized Test Procedure.
Latch up evaluation involves three separate stresses to evaluate latch up susceptibility levels:
1. dc current stressing of input and output pins.
2. Power supply slew rate.
3. Power supply overvoltage.
Table 7. Latch Up Test Criteria and Test Results
Data Transmission
Receiver ICs
Minimum Criteria
Test Results
dc Current Stress
of I/O Pins
150 mA
250 mA
Power Supply
Slew Rate
1 µs
100 ns
Power Supply
Overvoltage
1.75 x Vmax
2.25 x Vmax
Based on the results in Table 7, the data transmission receivers pass the Agere latch-up esting requirements and
are considered not susceptible to latch up.
Agere Systems Inc.
7

7페이지



구       성총 12 페이지
다운로드[ BRT1A16G.PDF 데이터시트 ]
구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

전력 반도체 판매 ( IGBT, TR 모듈, SCR, 다이오드 모듈 )

휴대전화 : 010-3582-2743


상호 : 아이지 인터내셔날

전화번호 : 051-319-2877, [ 홈페이지 ]



링크공유

링크 :

관련 데이터시트

부품번호상세설명 및 기능제조사
BRT1A16E

Quad Differential Receivers BRF1A/ BRF2A/ BRS2B/ BRR1A/ and BRT1A

Agere Systems
Agere Systems
BRT1A16E-TR

Quad Differential Receivers BRF1A/ BRF2A/ BRS2B/ BRR1A/ and BRT1A

Agere Systems
Agere Systems

DataSheet.kr    |   2019   |  연락처   |  링크모음   |   검색  |   사이트맵