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PDF BS616LV2018DI Data sheet ( Hoja de datos )
| Número de pieza | BS616LV2018DI | |
| Descripción | Very Low Power/Voltage CMOS SRAM 128K X 16 bit | |
| Fabricantes | Brilliance Semiconductor | |
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BSI Very Low Power/Voltage CMOS SRAM
128K X 16 bit
BS616LV2018
FEATURES
• Very low operation voltage : 2.4 ~ 3.6V
• Very low power consumption :
Vcc = 3.0V C-grade: 16mA (Max.) operating current
I -grade: 20mA (Max.) operating current
0.1uA (Typ.) CMOS standby current
• High speed access time :
-70 70ns (Max.) at Vcc = 3.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
PRODUCT FAMILY
DESCRIPTION
The BS616LV2018 is a high performance, very low power CMOS Static
Random Access Memory organized as 131,072 words by 16 bits and
operates from a wide range of 2.4V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.1uA and maximum access time of 70ns in 3V operation.
Easy memory expansion is provided by active LOW chip
enable(CE), active LOW output enable(OE) and three-state output
drivers.
The BS616LV2018 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV2018 is available in DICE form, JEDEC standard 48-pin
TSOP Type I package and 48-ball BGA package.
PRODUCT
FAM ILY
O P E R ATIN G
TE M P E R ATU R E
Vcc
RANGE
BS616LV2018DC
BS616LV2018TC
BS616LV2018AC
0 O C to +70 O C
BS616LV2018DI
BS616LV2018TI
-40 O C to +85 O C
BS616LV2018AI
PIN CONFIGURATIONS
2.4V ~3.6V
SPEED
(ns)
Vcc=
3.0V
70
POWER DISSIPATION
STANDBY
Operating
(ICCSB1, Max)
(ICC, Max)
Vcc=3.0V
Vcc=3.0V
0.7 uA
16 mA
70 1.5 uA
20 mA
BLOCK DIAGRAM
PKG TYPE
DICE
TSOP1-48
BGA-48-0608
DICE
TSOP1-48
BGA-48-0608
123456
A LB OE A0 A1 A2 N.C.
B D8 UB A3 A4 CE D0
C D9 D10 A5 A6 D1 D2
D
VSS D11 N.C.
A7
D3 VCC
E
VCC D12 N.C. A16
D4 VSS
F
D14 D13 A14 A15
D5
D6
G
D15 N.C. A12 A13 WE
D7
H
N.C.
A8
A9 A10 A11 N.C.
48-ball BGA top view
A8
A13
A15
A16
A14
A12
A7
A6
A5
A4
DQ0
.
.
.
.
DQ15
Address
Input
Buffer
20
Row
1024
Decoder
Data
16
Input
16
. Buffer
.
. 16
.
Data
Output
16
Buffer
Memory Array
1024 x 2048
2048
Column I/O
Write Driver
Sense Amp
128
Column Decoder
CE
WE
OE
UB
LB
Vcc
Gnd
Control
14
Address Input Buffer
A11 A9 A3 A2 A1 A0 A10
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS616LV2018
1
Revision 2.0
April 2002
1 page  
BSI
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
ADDRESS
D OUT
READ CYCLE2 (1,3,4)
t OH
t AA
t RC
BS616LV2018
t OH
CE
LB,UB
D OUT
t ACS
t BA
t (5)
CLZ
t BE
t tBDO
(5)
CHZ
READ CYCLE3 (1,4)
ADDRESS
t RC
t AA
OE
t OE
CE
LB,UB
t OLZ
t(5) ACS
t CLZ
t BA
t BE
D OUT
NOTES:
1. WE is high for read Cycle.
2. Device is continuously selected when CE = VIL.
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL .
5. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
t OH
t OHZ (5)
t (1,5)
CHZ
t BDO
R0201-BS616LV2018
5
Revision 2.0
April 2002
5 Page 
BSI
BS616LV2018
REVISION HISTORY
Revision
1.0
2.0
Description
Data Sheet release
Modify some AC parameters
Date
Note
Jan. 30, 2001
April,12,2002
R0201-BS616LV2018
11
Revision 2.0
April 2002
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet BS616LV2018DI.PDF ] | |
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