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BS616LV2025DC 데이터시트 PDF




Brilliance Semiconductor에서 제조한 전자 부품 BS616LV2025DC은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 BS616LV2025DC 기능
기능 Very Low Power/Voltage CMOS SRAM 128K x 16 or 256K x 8 bit switchable
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BS616LV2025DC 데이터시트, 핀배열, 회로
BSI Very Low Power/Voltage CMOS SRAM
128K x 16 or 256K x 8 bit switchable BS616LV2025
„ FEATURES
• Very low operation voltage : 4.5 ~ 5.5V
• Very low power consumption :
Vcc = 5.0V C-grade: 40mA (Max.) operating current
I -grade: 45mA (Max.) operating current
0.6uA (Typ.) CMOS standby current
• High speed access time :
-70 70ns (Max.) at Vcc = 5.0V
-55 55ns (Max.) at Vcc = 5.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE1, CE2 and OE options
• I/O Configuration x8/x16 selectable by CIO, LB and UB pin
„ DESCRIPTION
The BS616LV2025 is a high performance, very low power CMOS Static
Random Access Memory organized as 131,072 words by 16 bits or
262,144 bytes by 8 bits selectable by CIO pin and operates from a wide
range of 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.6uA and maximum access time of 70/55 ns in 5V operation.
Easy memory expansion is provided by active HIGH chip
enable2(CE2), active LOW chip enable1(CE1), active LOW output
enable(OE) and three-state output drivers.
The BS616LV2025 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV2025 is available in DICE form and 48-pin BGA type.
„ PRODUCT FAMILY
PRODUCT
FAMILY
BS616LV2025DC
BS616LV2025AC
BS616LV2025DI
BS616LV2025AI
OPERATING
TEMPERATURE
Vcc
RANGE
+0 O C to +70 O C 4.5V ~ 5.5V
-40 O C to +85 O C 4.5V ~ 5.5V
SPEED
( ns )
Vcc=5.0V
70 / 55
70 / 55
POWER DISSIPATION
STANDBY
Operating
( ICCSB1, Max )
( ICC, Max )
Vcc=5.0V
Vcc=5.0V
6uA 40mA
25uA
45mA
PKG TYPE
DICE
BGA-48-0608
DICE
BGA-48-0608
„ PIN CONFIGURATION
„ BLOCK DIAGRAM
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
Address
Input
Buffer
20
Row
1024
Decoder
D0
..
..
..
..
D15
16(8)
16(8)
Data
Input
Buffer
16(8)
16(8)
Data
Output
Buffer
Memory Array
1024 x 2048
2048
Column I/O
Write Driver
Sense Amp
128(256)
Column Decoder
CE1
CE2
WE
OE
UB
LB
CIO
Vdd
Vss
Control
14(16)
Address Input Buffer
A16 A0 A1 A2 A3 A4 A5 (SAE)
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS616LV2025
1
Revision 2.4
April 2002




BS616LV2025DC pdf, 반도체, 판매, 대치품
BSI
BS616LV2025
„ DC ELECTRICAL CHARACTERISTICS (TA = 0oC to +70oC)
PARAMETER
NAME
V IL
V IH
PARAMETER
Guaranteed Input Low
Voltage (2)
Guaranteed Input High
Voltage (2)
TEST CONDITIONS
MIN. TYP.(1) MAX.
Vcc=5.0V -0.5
--
0.8
Vcc=5.0V 2.2
-- Vcc+0.2
I IL Input Leakage Current Vcc = Max, VIN = 0V to Vcc
-- --
1
UNITS
V
V
uA
I OL
V OL
V OH
I CC
Output Leakage Current
Vcc = Max, CE1 = VIHor CE2=VILor OE = VIH,
VI/O = 0V to Vcc
Output Low Voltage
Output High Voltage
Vcc = Max, IOL= 2mA
Vcc = Min, IOH = -1mA
Vcc=5.0V
Vcc=5.0V
Operating Power Supply Vcc = Max, CE1= VIL, CE2=VIH
Current
IDQ = 0mA, F = Fmax (3)
Vcc=5.0V
--
--
2.4
--
--
--
--
--
1
0.4
--
40
uA
V
V
mA
I CCSB
Standby Current-TTL
Vcc = Max, CE1 = VIH or CE2=VIL
IDQ = 0mA
Vcc=5.0V
--
--
1
mA
I CCSB1
Standby Current-CMOS
Vcc = Max, CE1ЊVcc-0.2V or
CE2Љ0.2V,
Other inputsЊ Vcc - 0.2V or
VINЉ0.2V
Vcc=5.0V --
0.6 6
1. Typical characteristics are at TA = 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/tRC .
uA
R0201-BS616LV2025
4
Revision 2.4
April 2002

4페이지










BS616LV2025DC 전자부품, 판매, 대치품
BSI
„ SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
ADDRESS
D OUT
READ CYCLE2 (1,3,4)
t OH
t AA
CE2
CE1
D OUT
t ACS2
t ACS1
t (5)
CLZ
t RC
BS616LV2025
t OH
t (5)
CHZ
READ CYCLE3 (1,4)
ADDRESS
OE
CE2
CE1
LB, UB
t RC
t AA
t OE
t ACS2
t OLZ
t ACS1
t (5)
CLZ
t BE
t BA
t OH
t (5)
OHZ
t (1,5)
CHZ
t BDO
D OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2 = VIH.
3. Address valid prior to or coincident with CE1 transition low and CE2 transition high.
4. OE = VIL .
5. Transition is measured ± 500mV from steady state with CL = 30pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
R0201-BS616LV2025
7
Revision 2.4
April 2002

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부품번호상세설명 및 기능제조사
BS616LV2025DC

Very Low Power/Voltage CMOS SRAM 128K x 16 or 256K x 8 bit switchable

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Very Low Power/Voltage CMOS SRAM 128K x 16 or 256K x 8 bit switchable

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