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PDF BS616LV4010AI Data sheet ( Hoja de datos )
| Número de pieza | BS616LV4010AI | |
| Descripción | Very Low Power/Voltage CMOS SRAM 256K X 16 bit | |
| Fabricantes | Brilliance Semiconductor | |
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BSI Very Low Power/Voltage CMOS SRAM
256K X 16 bit
BS616LV4010
FEATURES
DESCRIPTION
• Very low operation voltage : 2.7 ~ 3.6V
• Very low power consumption :
Vcc = 3.0V C-grade: 20mA (Max.) operating current
I -grade: 25mA (Max.) operating current
0.5uA (Typ.) CMOS standby current
• High speed access time :
-70 70ns (Max.) at Vcc = 3.0V
-10 100ns (Max.) at Vcc = 3.0V
•Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
The BS616LV4010 is a high performance, very low power CMOS Static
Random Access Memory organized as 262,144 words by 16 bits and
operates from a wide range of 2.7V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.5uA and maximum access time of 70/100ns in 3V operation.
Easy memory expansion is provided by an active LOW chip
enable(CE) and active LOW output enable(OE) and three-state output
drivers.
The BS616LV4010 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV4010 is available in DICE form, JEDEC standard 44-pin
TSOP Type II package and 48-pin BGA package.
PRODUCT FAMILY
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
SPEED
( ns )
Vcc=3.0V
POWER DISSIPATION
STANDBY
Operating
( ICCSB1, Max )
( ICC, Max )
Vcc=3.0V
Vcc=3.0V
PKG TYPE
BS616LV4010DC
BS616LV4010EC
BS616LV4010AC
BS616LV4010BC
BS616LV4010DI
BS616LV4010EI
BS616LV4010AI
BS616LV4010BI
+0 O C to +70 O C 2.7V ~ 3.6V
-40 O C to +85 O C 2.7V ~ 3.6V
70 / 100
70 / 100
8uA
12uA
20mA
25mA
DICE
TSOP2-44
BGA-48-0608
BGA-48-0810
DICE
TSOP2-44
BGA-48-0608
BGA-48-0810
PIN CONFIGURATIONS
A4
A3
A2
A1
A0
CE
DQ0
DQ1
DQ2
DQ3
VCC
GND
DQ4
DQ5
DQ6
DQ7
WE
A17
A16
A15
A14
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
BS616LV4010EC
BS616LV4010EI
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
DQ15
DQ14
DQ13
DQ12
GND
VCC
DQ11
DQ10
DQ9
DQ8
NC
A8
A9
A10
A11
A12
BLOCK DIAGRAM
A4
A3
A2
A1
A0
A17
A16
A15
A14
A13
A12
DQ0
.
.
.
.
DQ15
Address
Input
Buffer
22
Row
2048
Decoder
Data
16
Input
16
. Buffer
.
. 16
.
Data
Output
16
Buffer
Memory Array
2048 x 2048
2048
Column I/O
Write Driver
Sense Amp
128
Column Decoder
CE
WE
OE
UB
LB
Vcc
Gnd
Control
14
Address Input Buffer
A11 A10 A9 A8 A7 A6 A5
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS616LV4010
1
Revision 2.3
April. 2002
1 page  
BSI
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
ADDRESS
D OUT
READ CYCLE2 (1,3,4)
t OH
t AA
t RC
BS616LV4010
t OH
CE
LB,UB
D OUT
t ACS
t BA
t (5)
CLZ
t BE
t tBDO
(5)
CHZ
READ CYCLE3 (1,4)
ADDRESS
t RC
t AA
OE
t OE
CE
LB,UB
t OLZ
t(5) ACS
t CLZ
t BA
t BE
D OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = VIL.
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL .
5. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
t OH
t OHZ (5)
t (1,5)
CHZ
t BDO
R0201-BS616LV4010
5
Revision 2.3
April. 2002
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet BS616LV4010AI.PDF ] | |
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