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BS616LV4010EC 데이터시트 PDF




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부품번호 BS616LV4010EC 기능
기능 Very Low Power/Voltage CMOS SRAM 256K X 16 bit
제조업체 Brilliance Semiconductor
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BS616LV4010EC 데이터시트, 핀배열, 회로
BSI Very Low Power/Voltage CMOS SRAM
256K X 16 bit
BS616LV4010
„ FEATURES
„ DESCRIPTION
• Very low operation voltage : 2.7 ~ 3.6V
• Very low power consumption :
Vcc = 3.0V C-grade: 20mA (Max.) operating current
I -grade: 25mA (Max.) operating current
0.5uA (Typ.) CMOS standby current
• High speed access time :
-70 70ns (Max.) at Vcc = 3.0V
-10 100ns (Max.) at Vcc = 3.0V
•Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
The BS616LV4010 is a high performance, very low power CMOS Static
Random Access Memory organized as 262,144 words by 16 bits and
operates from a wide range of 2.7V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.5uA and maximum access time of 70/100ns in 3V operation.
Easy memory expansion is provided by an active LOW chip
enable(CE) and active LOW output enable(OE) and three-state output
drivers.
The BS616LV4010 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV4010 is available in DICE form, JEDEC standard 44-pin
TSOP Type II package and 48-pin BGA package.
„ PRODUCT FAMILY
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
SPEED
( ns )
Vcc=3.0V
POWER DISSIPATION
STANDBY
Operating
( ICCSB1, Max )
( ICC, Max )
Vcc=3.0V
Vcc=3.0V
PKG TYPE
BS616LV4010DC
BS616LV4010EC
BS616LV4010AC
BS616LV4010BC
BS616LV4010DI
BS616LV4010EI
BS616LV4010AI
BS616LV4010BI
+0 O C to +70 O C 2.7V ~ 3.6V
-40 O C to +85 O C 2.7V ~ 3.6V
70 / 100
70 / 100
8uA
12uA
20mA
25mA
DICE
TSOP2-44
BGA-48-0608
BGA-48-0810
DICE
TSOP2-44
BGA-48-0608
BGA-48-0810
„ PIN CONFIGURATIONS
A4
A3
A2
A1
A0
CE
DQ0
DQ1
DQ2
DQ3
VCC
GND
DQ4
DQ5
DQ6
DQ7
WE
A17
A16
A15
A14
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
BS616LV4010EC
BS616LV4010EI
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
DQ15
DQ14
DQ13
DQ12
GND
VCC
DQ11
DQ10
DQ9
DQ8
NC
A8
A9
A10
A11
A12
„ BLOCK DIAGRAM
A4
A3
A2
A1
A0
A17
A16
A15
A14
A13
A12
DQ0
.
.
.
.
DQ15
Address
Input
Buffer
22
Row
2048
Decoder
Data
16
Input
16
. Buffer
.
. 16
.
Data
Output
16
Buffer
Memory Array
2048 x 2048
2048
Column I/O
Write Driver
Sense Amp
128
Column Decoder
CE
WE
OE
UB
LB
Vcc
Gnd
Control
14
Address Input Buffer
A11 A10 A9 A8 A7 A6 A5
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS616LV4010
1
Revision 2.3
April. 2002




BS616LV4010EC pdf, 반도체, 판매, 대치품
BSI
„ LOW VCC DATA RETENTION WAVEFORM ( CE Controlled )
BS616LV4010
Vcc
CE
Vcc
t CDR
VIH
Data Retention Mode
VDR 1.5V
CE Vcc - 0.2V
Vcc
tR
VIH
„ AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0V
5ns
0.5Vcc
„ KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
MUST BE
STEADY
OUTPUTS
MUST BE
STEADY
„ AC TEST LOADS AND WAVEFORMS
3.3V
OUTPUT
1269
3.3V
OUTPUT
1269
INCLUDING
JIG AND
SCOPE
100PF
1404
INCLUDING
JIG AND
SCOPE
5PF
1404
FIGURE 1A
FIGURE 1B
OUTPUT
THEVENIN EQUIVALENT
667
1.73V
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
DON , T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
ALL INPUT PULSES
Vcc
GND
10%
90% 90%
←→
10%
5ns
FIGURE 2
„ AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 3.0V )
READ CYCLE
JEDEC
PARAMETER
NAME
tAVAX
tAVQV
t
ELQV
tBA
tGLQV
tELQX
tBE
tGLQX
tEHQZ
tBDO
tGHQZ
tAXOX
PARAMETER
NAME
tRC
tAA
t
ACS
t (1)
BA
tOE
tCLZ
tBE
tOLZ
tCHZ
tBDO
tOHZ
tOH
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Data Byte Control to Output High Z
Output Disable to Output in High Z
Output Disable to Address Change
(CE)
(LB,UB)
(CE)
(LB,UB)
(CE)
(LB,UB)
BS616LV4010-70
MIN. TYP. MAX.
70 --
--
-- -- 70
-- -- 70
-- -- 35
-- -- 35
10 --
--
10 --
--
10 --
--
0 -- 35
0 -- 35
0 -- 30
10 --
--
BS616LV4010-10
MIN. TYP. MAX.
100 --
--
-- -- 100
-- -- 100
-- -- 50
-- -- 50
15 --
--
15 --
--
15 --
--
0 -- 40
0 -- 40
0 -- 35
15 --
--
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE :
1. tBA is 35ns/50ns (@speed=70ns/100ns) with address toggle. ; tBA is 70ns/100ns (@speed=70ns/100ns) without address toggle.
R0201-BS616LV4010
4
Revision 2.3
April. 2002

4페이지










BS616LV4010EC 전자부품, 판매, 대치품
BSI
WRITE CYCLE2 (1,6)
ADDRESS
CE
LB,UB
WE
D OUT
D IN
BS616LV4010
t WC
t AS
t (11)
CW
(5)
t AW
(4,10)
t WHZ
t BW
t WP
(2)
t DW
t WR
(3)
t DH
(7)
t DH
(8,9)
(8)
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. TWR is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE going low to the end of write.
R0201-BS616LV4010
7
Revision 2.3
April. 2002

7페이지


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