Datasheet.kr   

BS616LV4011DI 데이터시트 PDF




Brilliance Semiconductor에서 제조한 전자 부품 BS616LV4011DI은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 BS616LV4011DI 자료 제공

부품번호 BS616LV4011DI 기능
기능 Very Low Power/Voltage CMOS SRAM 256K X 16 bit
제조업체 Brilliance Semiconductor
로고 Brilliance Semiconductor 로고


BS616LV4011DI 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.



전체 10 페이지수

미리보기를 사용할 수 없습니다

BS616LV4011DI 데이터시트, 핀배열, 회로
BSI Very Low Power/Voltage CMOS SRAM
256K X 16 bit
BS616LV4011
„ FEATURES
• Very low operation voltage : 2.4 ~ 5.5V
• Very low power consumption :
Vcc = 3.0V C-grade: 20mA (Max.) operating current
I-grade: 25mA (Max.) operating current
0.25uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade: 45mA (Max.) operating current
I-grade: 50mA (Max.) operating current
1.5uA (Typ.) CMOS standby current
• High speed access time :
-70 70ns (Max.) at Vcc = 3.0V
-10 100ns (Max.) at Vcc = 3.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
„ DESCRIPTION
The BS616LV4011 is a high performance, very low power CMOS Static
Random Access Memory organized as 262,144 words by 16 bits and
operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.25uA and maximum access time of 70/100ns in 3V operation.
Easy memory expansion is provided by active LOW chip
enable(CE), active LOW output enable(OE) and three-state output
drivers.
The BS616LV4011 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV4011 is available in DICE form, JEDEC standard 44-pin
TSOP Type II package and 48-pin BGA package.
„ PRODUCT FAMILY
PRODUCT
FAMILY
BS616LV4011DC
BS616LV4011EC
BS616LV4011BC
BS616LV4011AC
BS616LV4011DI
BS616LV4011EI
BS616LV4011BI
BS616LV4011AI
OPERATING
TEMPERATURE
Vcc
RANGE
+0 O C to +70 O C 2.4V ~ 5.5V
-40 O C to +85 O C 2.4V ~ 5.5V
SPEED
( ns )
Vcc=
3.0V
70/100
70/100
POWER DISSIPATION
STANDBY
( ICCSB1, Max )
Operating
( ICC, Max )
Vcc=
3.0V
Vcc=
5.0V
Vcc=
3.0V
Vcc=
5.0V
1.5uA
15uA
20mA
45mA
3uA
50uA
25mA
50mA
PKG TYPE
DICE
TSOP2-44
BGA-48-0810
BGA-48-0608
DICE
TSOP2-44
BGA-48-0810
BGA-48-0608
„ PIN CONFIGURATIONS
A4 1
44 A5
A3 2
43 A6
A2 3
42 A7
A1 4
41 OE
A0 5
40 UB
CE 6
39 LB
DQ0
7
38 DQ15
DQ1
8
37 DQ14
DQ2
DQ3
9
10
BS616LV4011EC
36
35
DQ13
DQ12
VCC
GND
11
12
BS616LV4011EI
34 GND
33 VCC
DQ4
13
32 DQ11
DQ5
14
31 DQ10
DQ6
15
30 DQ9
DQ7
16
29 DQ8
WE 17
28 NC
A17 18
27 A8
A16 19
26 A9
A15 20
25 A10
A14 21
24 A11
A13 22
23 A12
„ BLOCK DIAGRAM
A4
A3
A2
A1
A0
A17
A16
A15
A14
A13
A12
DQ0
.
.
.
.
DQ15
Address
Input
Buffer
22
Row
2048
Decoder
Data
16
Input
16
. Buffer
.
. 16
.
Data
Output
16
Buffer
Memory Array
2048 x 2048
2048
Column I/O
Write Driver
Sense Amp
128
Column Decoder
CE
WE
OE
UB
LB
Vcc
Gnd
Control
14
Address Input Buffer
A11 A10 A9 A8 A7 A6 A5
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS616LV4011
1
Revision 2.4
April 2002




BS616LV4011DI pdf, 반도체, 판매, 대치품
BSI
„ LOW VCC DATA RETENTION WAVEFORM ( CE Controlled )
Vcc
CE
Vcc
t CDR
VIH
Data Retention Mode
VDR 1.5V
CE Vcc - 0.2V
BS616LV4011
Vcc
tR
VIH
„ AC TEST CONDITIONS
„ KEY TO SWITCHING WAVEFORMS
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0V
5ns
0.5Vcc
„ AC TEST LOADS AND WAVEFORMS
3.3V
OUTPUT
1269
3.3V
OUTPUT
1269
INCLUDING
JIG AND
SCOPE
100PF
1404
INCLUDING
JIG AND
SCOPE
5PF
1404
FIGURE 1A
FIGURE 1B
OUTPUT
THEVENIN EQUIVALENT
667
1.73V
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
DON , T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
OUTPUTS
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
ALL INPUT PULSES
Vcc
GND
10%
90% 90%
←→
10%
5ns
FIGURE 2
„ AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 3.0V )
READ CYCLE
JEDEC
PARAMETER
NAME
t
AVAX
t
AVQV
t
ELQV
t
BA
t
GLQV
t
ELQX
t
BE
t
GLQX
t
EHQZ
t
BDO
t
GHQZ
t
AXOX
PARAMETER
NAME
t
RC
t
AA
t
ACS
t
BA
(1)
t
OE
t
CLZ
t
BE
t
OLZ
t
CHZ
t
BDO
t
OHZ
t
OH
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Data Byte Control to Output High Z
Output Disable to Output in High Z
Output Disable to Address Change
(CE)
(LB,UB)
(CE)
(LB,UB)
(CE)
(LB,UB)
BS616LV4011-70
MIN. TYP. MAX.
70 --
--
-- -- 70
-- -- 70
-- -- 35
-- -- 35
10 --
--
10 --
--
10 --
--
0 -- 35
0 -- 35
0 -- 30
10 --
--
BS616LV4011-10
MIN. TYP. MAX.
100 --
--
-- -- 100
-- -- 100
-- -- 50
-- -- 50
15 --
--
15 --
--
15 --
--
0 -- 40
0 -- 40
0 -- 35
15 --
--
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE :
1. tBA is 35ns/50ns (@speed=70ns/100ns) with address toggle. ; tBA is 70ns/100ns (@speed=70ns/100ns) without address toggle.
R0201-BS616LV4011
4
Revision 2.4
April 2002

4페이지










BS616LV4011DI 전자부품, 판매, 대치품
BSI
WRITE CYCLE2 (1,6)
ADDRESS
CE
LB,UB
WE
D OUT
D IN
BS616LV4011
t WC
t AS
t (11)
CW
(5)
t AW
(4,10)
t WHZ
t BW
t WP
(2)
t DW
t WR
(3)
t DH
(7)
t DH
(8,9)
(8)
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. TWR is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE going low to the end of write.
R0201-BS616LV4011
7
Revision 2.4
April 2002

7페이지


구       성 총 10 페이지수
다운로드[ BS616LV4011DI.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
BS616LV4011DC

Very Low Power/Voltage CMOS SRAM 256K X 16 bit

Brilliance Semiconductor
Brilliance Semiconductor
BS616LV4011DI

Very Low Power/Voltage CMOS SRAM 256K X 16 bit

Brilliance Semiconductor
Brilliance Semiconductor

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵