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PDF BS616LV4021BC Data sheet ( Hoja de datos )
| Número de pieza | BS616LV4021BC | |
| Descripción | Very Low Power/Voltage CMOS SRAM 256K x 16 or 512K x 8 bit switchable | |
| Fabricantes | Brilliance Semiconductor | |
| Logotipo |  |
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BSI Very Low Power/Voltage CMOS SRAM
256K x 16 or 512K x 8 bit switchable BS616LV4021
FEATURES
• Very low operation voltage : 2.4 ~ 5.5V
• Very low power consumption :
Vcc = 3.0V C-grade: 20mA (Max.) operating current
I-grade : 25mA (Max.) operating current
0.25uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade: 45mA (Max.) operating current
I-grade : 50mA (Max.) operating current
1.5uA (Typ.) CMOS standby current
• High speed access time :
-70 70ns (Max.) at Vcc=3.0V
-10 100ns (Max.) at Vcc=3.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE1, CE2 and OE options
• I/O Configuration x8/x16 selectable by CIO, LB and UB pin
PRODUCT FAMILY
DESCRIPTION
The BS616LV4021 is a high performance, very low power CMOS Static
Random Access Memory organized as 262,144words by 16 bits or
524,288 bytes by 8 bits selectable by CIO pin and operates from a wide
range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.25uA and maximum access time of 70/100ns in 3V operation.
Easy memory expansion is provided by active HIGH chip
enable2(CE2), active LOW chip enable1(CE1), active LOW output
enable(OE) and three-state output drivers.
The BS616LV4021 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV4021 is available in DICE form and 48-ball BGA type.
PRODUCT
FAMILY
BS616LV4021DC
BS616LV4021BC
BS616LV4021DI
BS616LV4021BI
OPERATING
TEMPERATURE
Vcc
RANGE
+0 O C to +70 O C 2.4V ~ 5.5V
-40 O C to +85 O C 2.4V ~ 5.5V
SPEED
(ns)
Vcc=3.0V
70 / 100
70 / 100
POWER DISSIPATION
STANDBY
(ICCSB1, Max)
Operating
(ICC, Max)
Vcc=
3.0V
Vcc=
5.0V
Vcc=
3.0V
Vcc=
5.0V
1.5uA 15uA 20mA 45mA
3uA 50uA 25mA 50mA
PKG TYPE
DICE
BGA-48-0810
DICE
BGA-48-0810
PIN CONFIGURATION
BLOCK DIAGRAM
A15
A14
A13
A12
A11
A10
A9
A8
A17
A7
A6
D0
.
.
.
.
D15
Address
Input
Buffer
22
Row
2048
Decoder
16(8)
.
.
. 16(8)
.
Data
Input
Buffer
16(8)
16(8)
Data
Output
Buffer
Memory Array
2048 x 2048
2048
Column I/O
Write Driver
Sense Amp
128(256)
Column Decoder
CE1
CE2
WE
OE
UB
LB
CIO
Vdd
Vss
Control
14(16)
Address Input Buffer
A16 A0 A1 A2 A3 A4 A5 (SAE)
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS616LV4021
1
Revision 2.4
April 2002
1 page  
BSI
DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70oC )
SYMBOL
PARAMETER
TEST CONDITIONS
VDR Vcc for Data Retention
CE1 Њ Vcc - 0.2V or CE2 Љ 0.2V ;
VIN Њ Vcc - 0.2V or VIN Љ 0.2V
ICCDR
tCDR
tR
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
CE1 Њ Vcc - 0.2V or CE2 Љ 0.2V
VIN Њ Vcc - 0.2V or VIN Љ 0.2V
See Retention Waveform
1. Vcc = 1.5V, TA = + 25OC
2. tRC = Read Cycle Time
LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled )
Vcc
CE1
Vcc
t CDR
VIH
Data Retention Mode
VDR Њ 1.5V
CE1 Њ Vcc - 0.2V
BS616LV4021
MIN. TYP. (1) MAX.
1.5 --
--
UNITS
V
-- 0.1
0
TRC (2)
--
--
1
--
--
uA
ns
ns
Vcc
tR
VIH
LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled )
Vcc
CE2
Vcc
t CDR
VIL
Data Retention Mode
VDR Њ 1.5V
CE2 Љ 0.2V
Vcc
tR
VIL
R0201-BS616LV4021
5
Revision 2.4
April 2002
5 Page 
BSI
BS616LV4021
REVISION HISTORY
Revision
2.2
2.3
2.4
Description
2001 Data Sheet release
Date
Apr. 15, 2001
Modify Standby Current (Typ. and Jun. 29, 2001
Max.)
Modify some AC parameters.
Modify 5V ICCSB1_Max(I-grade)
from 25uA to 50uA.
April,11,2002
Note
R0201-BS616LV4021
11
Revision 2.4
April 2002
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet BS616LV4021BC.PDF ] | |
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