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BS616LV8011 데이터시트 PDF




Brilliance Semiconductor에서 제조한 전자 부품 BS616LV8011은 전자 산업 및 응용 분야에서
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부품번호 BS616LV8011 기능
기능 Very Low Power/Voltage CMOS SRAM 512K X 16 bit
제조업체 Brilliance Semiconductor
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BS616LV8011 데이터시트, 핀배열, 회로
BSI Very Low Power/Voltage CMOS SRAM
512K X 16 bit
BS616LV8011
„ FEATURES
• Very low operation voltage : 2.7 ~ 3.6V
• Very low power consumption :
Vcc = 3.0V C-grade: 40mA (Max.) operating current
I-grade : 50mA (Max.) operating current
1uA (Typ.) CMOS standby current
• High speed access time :
-70 70ns (Max.) at Vcc=3.0V
-10 100ns (Max.) at Vcc=3.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE1,CE2 and OE options
„ DESCRIPTION
The BS616LV8011 is a high performance, very low power CMOS Static
Random Access Memory organized as 524,288 words by 16 bits and
operates from a wide range of 2.7V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 1uA and maximum access time of 70/100ns in 3V operation.
Easy memory expansion is provided by an active LOW chip
enable(CE1,CE2) and active LOW output enable(OE) and three-state
output drivers.
The BS616LV8011 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV8011 is available in 48-pin BGA package.
„ PRODUCT FAMILY
PRODUCT FAMILY
BS616LV8011AC
BS616LV8011AI
OPERATING
TEMPERATURE
Vcc
RANGE
+0 O C to +70 O C 2.7V ~ 3.6V
-40 O C to +85 O C 2.7V ~ 3.6V
SPEED
(ns)
Vcc=3.0V
70 / 100
70 / 100
POWER DISSIPATION
STANDBY
(ICCSB1, Max)
Operating
(ICC, Max)
Vcc=3.0V
Vcc=3.0V
16uA
40mA
24uA
50mA
PKG TYPE
BGA-48-0608
BGA-48-0608
„ PIN CONFIGURATIONS
„ BLOCK DIAGRAM
123456
A X OE A0 A1 A2 CE2
B D8
X A3 A4 CE1 D0
C D9 D10 A5 A6 D1 D2
D VSS D11 A17 A7 D3 VCC
E VCC D12 Vss A16 D4 VSS
F D14 D13 A14 A15 D5 D6
G D15 NC. A12 A13 WE D7
H A18 A8 A9 A10 A11 NC.
48-Ball CSP top View
X: Don’t care
A4
A3
A2
A1
A0
A17
A16
A15
A14
A13
A12
D0
.
.
.
.
D15
Address
Input
Buffer
22
Row
2048
Decoder
Data
16
Input
16
. Buffer
.
. 16
.
Data
Output
16
Buffer
Memory Array
2048 x 4096
4096
Column I/O
Write Driver
Sense Amp
256
Column Decoder
CE1
CE2
OE
WE
Vcc
Gnd
Control
16
Address Input Buffer
A11 A10 A9 A8 A7 A6 A5 A18
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS616LV8011
1
Revision 2.3
April 2002




BS616LV8011 pdf, 반도체, 판매, 대치품
BSI
„ AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0V
5ns
0.5Vcc
„ AC TEST LOADS AND WAVEFORMS
3.3V
OUTPUT
1269
3.3V
OUTPUT
1269
INCLUDING
JIG AND
SCOPE
100PF
1404
INCLUDING
JIG AND
SCOPE
5PF
1404
FIGURE 1A
FIGURE 1B
OUTPUT
THEVENIN EQUIVALENT
667
1.73V
ALL INPUT PULSES
Vcc
GND
10%
90% 90%
←→
FIGURE 2
10%
5ns
BS616LV8011
„ KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
DON , T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
OUTPUTS
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FCRHOAMNGLET:O H
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
„ AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC, Vcc=3V )
READ CYCLE
JEDEC
PARAMETER
NAME
t
AVAX
t
AVQV
t
ELQV1
t
ELQV2
t
GLQV
t
ELQX
t
GLQX
t
EHQZ
t
GHQZ
t
AXOX
PARAMETER
NAME
DESCRIPTION
t
RC
t
AA
t
ACS1
t
ACS2
t
OE
t
CLZ
t
OLZ
t
CHZ
t
OHZ
t
OH
Read Cycle Time
Address Access Time
Chip Select Access Time
(CE1)
Chip Select Access Time
(CE2)
Output Enable to Output Valid
Chip Select to Output Low Z (CE2,CE1)
Output Enable to Output in Low Z
Chip Deselect to Output in High Z(CE2,CE1)
Output Disable to Output in High Z
Output Disable to Address Change
BS616LV8011-70
MIN. TYP. MAX.
70 -- --
-- -- 70
-- -- 70
-- -- 70
-- -- 35
10 -- --
10 -- --
0 -- 40
0 -- 35
10 -- --
BS616LV8011-10
MIN. TYP. MAX.
100 --
-- --
-- --
-- --
-- --
15 --
15 --
0 --
0 --
--
100
100
100
50
--
--
45
40
15 --
--
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R0201-BS616LV8011
4
Revision 2.3
April 2002

4페이지










BS616LV8011 전자부품, 판매, 대치품
BSI
WRITE CYCLE2 (1,6)
ADDRESS
CE2
CE1
WE
D OUT
D IN
BS616LV8011
t WC
t AS
(5)
t AW
(4,10)
t WHZ
(11)
t CW
t WP
(2)
t DW
t WR
(3)
t DH
(7)
t DH
(8,9)
(8)
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low.
All signals must be active to initiate a write and any one signal can terminate
a write by going inactive. The data input setup and hold timing should be referenced to the
second transition edge of the signal that terminates the write.
3. TWR is measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite
phase to the outputs must not be applied.
5. If the CE2 high transition or CE1 low transition occurs simultaneously with the WE low transitions
or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the
data input signals of opposite phase to the outputs must not be applied to them.
10. Transition is measured ± 500mV from steady state with CL = 30pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE2 going high or CE1 going low to the end of write.
R0201-BS616LV8011
7
Revision 2.3
April 2002

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부품번호상세설명 및 기능제조사
BS616LV8010

Very Low Power/Voltage CMOS SRAM 512K X 16 bit

Brilliance Semiconductor
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BS616LV8011

Very Low Power/Voltage CMOS SRAM 512K X 16 bit

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