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PDF BS616LV8015BI Data sheet ( Hoja de datos )
| Número de pieza | BS616LV8015BI | |
| Descripción | Very Low Power/Voltage CMOS SRAM 512K X 16 bit | |
| Fabricantes | Brilliance Semiconductor | |
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BSI Very Low Power/Voltage CMOS SRAM
512K X 16 bit
BS616LV8015
FEATURES
• Very low operation voltage : 4.5~5.5V
• Very low power consumption :
Vcc = 5.0V C-grade: 45mA (Max.) operating current
I-grade : 50mA (Max.) operating current
3uA (Typ.) CMOS standby current
• High speed access time :
-55 70ns (Max.) at Vcc=5V
-70 70ns (Max.) at Vcc=5V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE1,CE2 and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
DESCRIPTION
The BS616LV8015 is a high performance, very low power CMOS Static
Random Access Memory organized as 524,288 words by 16 bits and
operates from a wide range of 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 3uA and maximum access time of 55/70ns in 5V operation.
Easy memory expansion is provided by an active LOW chip enable(CE1),
active HIGH chip enable (CE2), active LOW output enable(OE) and
three-state output drivers.
The BS616LV8015 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV8015 is available in 48-pin BGA package.
PRODUCT FAMILY
PRODUCT FAMILY
BS616LV8015BC
BS616LV8015BI
OPERATING
TEMPERATURE
Vcc
RANGE
+0 O C to +70 O C 4.5V ~ 5.5V
-40 O C to +85 O C 4.5V ~ 5.5V
SPEED
(ns)
Vcc=5V
55 / 70
55 / 70
POWER DISSIPATION
STANDBY
(ICCSB1, Max)
Operating
(ICC, Max)
Vcc=5V
Vcc=5V
30uA
45mA
100uA
50mA
PKG TYPE
BGA-48-0810
BGA-48-0810
PIN CONFIGURATIONS
BLOCK DIAGRAM
123456
A LB OE A0 A1 A2 CE2
B D8 UB A3 A4 CE1 D0
C D9 D10 A5 A6 D1 D2
D VSS D11 A17 A7 D3 VCC
E VCC D12 VSS A16 D4 VSS
F D14 D13 A14 A15 D5 D6
G D15 N.C A12 A13 WE D7
H A18 A8 A9 A10 A11 NC
48-Ball CSP top View
A4
A3
A2
A1
A0
A17
A16
A15
A14
A13
A12
D0
.
.
.
.
D15
Address
Input
Buffer
22
Row
2048
Decoder
Data
16
Input
16
. Buffer
.
. 16
.
Data
Output
16
Buffer
Memory Array
2048 x 4096
4096
Column I/O
Write Driver
Sense Amp
256
Column Decoder
CE2
CE1
WE
OE
UB
LB
Vcc
Gnd
Control
16
Address Input Buffer
A11 A10 A9 A8 A7 A6 A5 A18
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS616LV8015
1
Revision 2.4
April 2002
1 page  
BSI
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
ADDRESS
D OUT
READ CYCLE2 (1,3,4)
CE2
CE1
D OUT
t OH
t AA
t ACS2
t ACS1
t (5)
CLZ
t RC
BS616LV8015
t OH
t (5)
CHZ
READ CYCLE3 (1,4)
ADDRESS
OE
CE2
CE1
LB,UB
t RC
t AA
t OE
t ACS2
t OLZ
t ACS1
t (5)
CLZ
t BE
t BA
t OH
t (5)
OHZ
t (1,5)
CHZ
t BDO
D OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2 = VIH.
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL .
5. Transition is measured ±500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
R0201-BS616LV8015
5
Revision 2.4
April 2002
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet BS616LV8015BI.PDF ] | |
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