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BS616UV1010 데이터시트 PDF




Brilliance Semiconductor에서 제조한 전자 부품 BS616UV1010은 전자 산업 및 응용 분야에서
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부품번호 BS616UV1010 기능
기능 Ultra Low Power/Voltage CMOS SRAM 64K X 16 bit
제조업체 Brilliance Semiconductor
로고 Brilliance Semiconductor 로고


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BS616UV1010 데이터시트, 핀배열, 회로
BSI Ultra Low Power/Voltage CMOS SRAM
64K X 16 bit
BS616UV1010
„ FEATURES
• Ultra low operation voltage : 1.8 ~ 3.6V
• Ultra low power consumption :
Vcc = 2.0V C-grade : 10mA (Max.) operating current
I- grade : 15mA (Max.) operating current
0.01uA (Typ.) CMOS standby current
Vcc = 3.0V C-grade : 15mA (Max.) operating current
I- grade : 20mA (Max.) operating current
0.02uA (Typ.) CMOS standby current
• High speed access time :
-15 150ns (Max.) at Vcc = 3.0V
• Input levels are CMOS-compatible
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
„ DESCRIPTION
The BS616UV1010 is a high performance, ultra low power CMOS Static
Random Access Memory organized as 65,536 words by 16 bits and
operates from a wide range of 1.8V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.01uA and maximum access time of 150ns in 2V operation.
Easy memory expansion is provided by an active LOW chip
enable(CE) and active LOW output enable(OE) and three-state output
drivers.
The BS616UV1010 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616UV1010 is available in the JEDEC standard 44-pin TSOP
Type II and 48-pin mini-BGA.
„ PRODUCT FAMILY
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
SPEED
(ns)
Vcc=3.0V
POWER DISSIPATION
STANDBY
Operating
(ICCSB1, Max)
(ICC, Max)
Vcc=3.0V Vcc=2.0V Vcc=3.0V Vcc=2.0V
PKG TYPE
BS616UV1010EC
BS616UV1010AC
+0 O C to +70 O C 1.8V ~ 3.6V
BS616UV1010EI
BS616UV1010AI
-40 O C to +85 O C 1.8V ~ 3.6V
„ PIN CONFIGURATIONS
A4
A3
A2
A1
A0
CE
DQ0
DQ1
DQ2
DQ3
VCC
GND
DQ4
DQ5
DQ6
DQ7
WE
A15
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
1
BS616UV1010EC
BS616UV1010EI
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
DQ15
DQ14
DQ13
DQ12
GND
VCC
DQ11
DQ10
DQ9
DQ8
NC
A8
A9
A10
A11
NC
23456
A LB OE A0 A1 A2 NC
B IO8 UB A3 A4 CE IO0
C IO9 IO10 A5 A6 IO1 IO2
D VSS IO11 NC A7 IO3 VCC
E VCC IO12 NC NC IO4 VSS
F IO14 IO13 A14 A15 IO5 IO6
150
0.5uA
0.3uA
15mA
150 1.5uA 1uA
„ BLOCK DIAGRAM
20mA
10mA
15mA
TSOP2-44
BGA-48-0608
TSOP2-44
BGA-48-0608
A8
A13
A15
A14
A12
Address
Input
18
Row
512
A7 Buffer
A6
Decoder
A5
A4
DQ0
..
16
Data
Input
Buffer
16
..
..
16
..
Data
Output
16
DQ15
Buffer
Memory Array
512 x 2048
2048
Column I/O
Write Driver
Sense Amp
128
Column Decoder
CE
WE
OE
UB
LB
Vcc
Gnd
Control
14
Address Input Buffer
A11 A9 A3 A2 A1 A0 A10
G IO15 NC A12 A13 WE IO7
H
NC A8
A9 A10 A11 NC
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS616UV1010
1
Revision 2.2
April 2001




BS616UV1010 pdf, 반도체, 판매, 대치품
BSI
„ LOW VCC DATA RETENTION WAVEFORM ( CE Controlled )
Vcc
CE
Vcc
t CDR
VIH
Data Retention Mode
VDR 1.5V
CE Vcc - 0.2V
BS616UV1010
Vcc
tR
VIH
„ AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0V
5ns
0.5Vcc
„ KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
MUST BE
STEADY
OUTPUTS
MUST BE
STEADY
„ AC TEST LOADS AND WAVEFORMS
1333
2V
2V
OUTPUT
OUTPUT
1333
INCLUDING
JIG AND
SCOPE
100PF
2000
INCLUDING
JIG AND
SCOPE
5PF
2000
FIGURE 1A
FIGURE 1B
OUTPUT
THEVENIN EQUIVALENT
800
1.2V
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
DON , T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
Vcc
GND
ALL INPUT PULSES
10%
90% 90%
←→
FIGURE 2
10%
5ns
„ AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC, Vcc = 2.0V )
READ CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
BS616UV1010-15
MIN. TYP. MAX.
tAVAX
tAVQV
tELQV
tBA
tGLQV
tELQX
tBE
tGLQX
tEHQZ
tBDO
tGHQZ
tRC
tAA
t ACS
tBA
tOE
tCLZ
tBE
tOLZ
tCHZ
tBDO
tOHZ
Read Cycle Time
150 --
--
Address Access Time
-- -- 150
Chip Select Access Time
(CE)
--
-- 150
Data Byte Control Access Time
(LB,UB)
--
-- 150
Output Enable to Output Valid
-- -- 80
Chip Select to Output Low Z
(CE) 15
--
--
Data Byte Control to Output Low Z (LB,UB)
15
--
--
Output Enable to Output in Low Z
15 --
--
Chip Deselect to Output in High Z
(CE)
0
-- 45
Data Byte Control to Output High Z (LB,UB)
0
-- 40
Output Disable to Output in High Z
0 -- 40
tAXOX
tOH Output Disable to Output Address Change
15 --
--
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R0201-BS616UV1010
4
Revision 2.2
April 2001

4페이지










BS616UV1010 전자부품, 판매, 대치품
BSI
WRITE CYCLE2 (1,6)
ADDRESS
CE
LB,UB
WE
D OUT
D IN
BS616UV1010
t WC
t AS
t (11)
CW
(5)
t AW
(4,10)
t WHZ
t BW
t WP
(2)
t DW
t WR
(3)
t DH
(7)
t DH
(8,9)
(8)
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. TWR is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE going low to the end of write.
12. The change of Read/Write cycle must accompany with CE or address toggled.
R0201-BS616UV1010
7
Revision 2.2
April 2001

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