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BS616UV1610FC 데이터시트 PDF




Brilliance Semiconductor에서 제조한 전자 부품 BS616UV1610FC은 전자 산업 및 응용 분야에서
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부품번호 BS616UV1610FC 기능
기능 Ultra Low Power/Voltage CMOS SRAM 1M X 16 bit
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BS616UV1610FC 데이터시트, 핀배열, 회로
BSI Ultra Low Power/Voltage CMOS SRAM
1M X 16 bit
BS616UV1610
„ FEATURES
• Ultra low operation voltage : 1.8 ~ 2.3V
• Ultra low power consumption :
Vcc = 2.0V C-grade: 25mA (Max.) operating current
I-grade : 30mA (Max.) operating current
1.2uA (Typ.) CMOS standby current
• High speed access time :
-70 70ns (Max.) at Vcc=2V
-10 100ns (Max.) at Vcc=2V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE2,CE1 and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
„ DESCRIPTION
The BS616UV1610 is a high performance, ultra low power CMOS Static
Random Access Memory organized as 1,048,576 words by 16 bits and
operates from a wide range of 1.8V to 2.3V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 1.2uA and maximum access time of 70/100ns in 2V operation.
Easy memory expansion is provided by an active LOW chip enable(CE1),
active HIGH chip enable (CE2), active LOW output enable(OE) and
three-state output drivers.
The BS616UV1610 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616UV1610 is available in 48-pin BGA package.
„ PRODUCT FAMILY
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
SPEED
(ns)
Vcc=2V
BS616UV1610BC
BS616UV1610FC
BS616UV1610BI
BS616UV1610FI
+0O C to +70OC
-40O C to +85OC
1.8 ~ 2.3V
1.8 ~ 2.3V
70 / 100
70 / 100
POWER DISSIPATION
STANDBY
(ICCSB1 , Max)
Operating
(I CC , Max)
Vcc=2V
Vcc=2V
30uA
25mA
40uA
30mA
PKG TYPE
BGA - 48- 0810
BGA - 48- 0912
BGA - 48- 0810
BGA - 48- 0912
„ PIN CONFIGURATIONS
„ BLOCK DIAGRAM
123456
A LB OE A0 A1 A2 CE2
B D8 UB A3 A4 CE1 D0
C D9 D10 A5 A6 D1 D2
D VSS D11 A17 A7 D3 VCC
E VCC D12 VSS A16 D4 VSS
F D14 D13 A14 A15 D5 D6
G D15 NC. A12 A13 WE D7
H A18 A8 A9 A10 A11 A1. 9
48-Ball CSP top View
A4
A3
A2
A1
A0
A17
A16
A15
A14
A13
A12
D0
.
.
.
.
D15
Address
Input
Buffer
22
Row
2048
Decoder
Data
16
Input
16
. Buffer
.
. 16
.
Data
Output
16
Buffer
Memory Array
2048 x 8192
8192
Column I/O
Write Driver
Sense Amp
512
Column Decoder
CE2
CE1
WE
OE
UB
LB
Vcc
Gnd
Control
18
Address Input Buffer
A11A10A9 A8 A7 A6 A5 A18 A19
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS616UV1610
1
Revision 2.2
April 2001




BS616UV1610FC pdf, 반도체, 판매, 대치품
BSI
BS616UV1610
„ AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0V
5ns
0.5Vcc
„ KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
MUST BE
STEADY
OUTPUTS
MUST BE
STEADY
„ AC TEST LOADS AND WAVEFORMS
2V
OUTPUT
1333
2V
OUTPUT
1333
INCLUDING
JIG AND
SCOPE
100PF
2000
INCLUDING
JIG AND
SCOPE
5PF
2000
FIGURE 1A
FIGURE 1B
OUTPUT
THEVENIN EQUIVALENT
800
1.2V
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
DON , T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
ALL INPUT PULSES
Vcc
GND
10%
90% 90%
←→
10%
5ns
FIGURE 2
„ AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC, Vcc=2V)
READ CYCLE
JEDEC
PARAMETER
NAME
t
AVAX
t
AVQV
t
ELQV
t
ELQV
t
BA
t
GLQV
t
ELQX
t
BE
t
GLQX
t
EHQZ
t
BDO
t
GHQZ
t
AXOX
PARAMETER
NAME
t
RC
t
AA
t
ACS1
t
ACS2
t
BA
t
OE
t
CLZ
t
BE
t
OLZ
t
CHZ
t
BDO
t
OHZ
t
OH
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
(CE1)
Chip Select Access Time
(CE2)
Data Byte Control Access Time
(LB,UB)
Output Enable to Output Valid
Chip Select to Output Low Z
(CE2,CE1)
Data Byte Control to Output Low Z (LB,UB)
Output Enable to Output in Low Z
Chip Deselect to Output in High Z (CE2,CE1)
Data Byte Control to Output High Z (LB,UB)
Output Disable to Output in High Z
Output Disable to Address Change
BS616UV1610-70
MIN. TYP. MAX.
70 --
--
-- -- 70
-- -- 70
-- -- 70
-- -- 50
-- -- 50
10 --
--
10 --
--
10 --
--
0 -- 35
0 -- 30
0 -- 30
10 --
--
BS616UV1610-100
MIN. TYP. MAX.
100 --
--
-- -- 100
-- -- 100
-- -- 100
-- -- 60
-- -- 60
15 --
--
15 --
--
15 --
--
0 -- 40
0 -- 35
0 -- 35
15 --
--
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R0201-BS616UV1610
4
Revision 2.2
April 2001

4페이지










BS616UV1610FC 전자부품, 판매, 대치품
BSI
WRITE CYCLE2 (1,6)
ADDRESS
BS616UV1610
t WC
CE2
CE1
LB,UB
WE
D OUT
D IN
t AS
(11)
t CW
(5)
t BW
(5)
t AW
(4,10)
t WHZ
t WP
(2)
t DW
t WR (3)
t DH
(7)
t DH
(8,9)
(8)
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. TWR is measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE2 high transition or CE1 low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE2 going high or CE1 going low to the end of write.
R0201-BS616UV1610
7
Revision 2.2
April 2001

7페이지


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