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BS616UV2011EC 데이터시트 PDF




Brilliance Semiconductor에서 제조한 전자 부품 BS616UV2011EC은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 BS616UV2011EC 기능
기능 Ultra Low Power/Voltage CMOS SRAM 128K X 16 bit
제조업체 Brilliance Semiconductor
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BS616UV2011EC 데이터시트, 핀배열, 회로
BSI Ultra Low Power/Voltage CMOS SRAM
128K X 16 bit
BS616UV2011
„ FEATURES
• Ultra low operation voltage : 1.8 ~ 3.6V
• Ultra low power consumption :
Vcc = 2.0 V C-grade: 15mA (Max.) operating current
I-grade: 20mA (Max.) operating current
0.08uA (Typ.) CMOS standby current
Vcc = 3.0 V C-grade: 20mA (Max.) operating current
I -grade: 25mA (Max.) operating current
0.1uA (Typ.) CMOS standby current
• High speed access time :
-70 70ns (Max.) at Vcc = 2.0V
-10 100ns (Max.) at Vcc = 2.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
„ PRODUCT FAMILY
„ DESCRIPTION
The BS616UV2011 is a high performance, Ultra low power CMOS Static
Random Access Memory organized as 131,072 words by 16 bits and
operates from a wide range of 1.8V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.08uA and maximum access time of 70/100ns in 2.0V operation.
Easy memory expansion is provided by an active LOW chip
enable(CE), active LOW output enable(OE) and three-state output
drivers.
The BS616UV2011 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616UV2011 is available in DICE form, JEDEC standard 44-pin
TSOP Type II package , JEDEC standard 48-pin TSOP Type I package
and 48-ball BGA package.
PRODUCT
FAMILY
BS616UV2011DC
BS616UV2011EC
BS616UV2011TC
BS616UV2011AC
BS616UV2011DI
BS616UV2011EI
BS616UV2011TI
BS616UV2011AI
OPERATING
TEMPERATURE
Vcc
RANGE
+0O C to +70OC 1.8V ~ 3.6V
-40O C to +85OC 1.8V ~ 3.6V
SPEED
( ns )
Vcc=
2.0V
70/100
70/100
POWER DISSIPATION
STANDBY
( I CCSB1, Max )
Operating
( I CC , Max )
Vcc=
2.0V
Vcc=
3.0V
Vcc=
2.0V
Vcc=
3.0V
0.5uA
0.7uA 15mA
20mA
1uA 1.5uA 20mA 25mA
PKG TYPE
DICE
TSOP2-44
TSOP1-48
BGA-48-0608
DICE
TSOP2-44
TSOP1-48
BGA-48-0608
„ PIN CONFIGURATIONS
A4
A3
A2
A1
A0
CE
DQ0
DQ1
DQ2
DQ3
VCC
GND
DQ4
DQ5
DQ6
DQ7
WE
A16
A15
A14
A13
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
BS616UV2011EC
BS616UV2011EI
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
DQ15
DQ14
DQ13
DQ12
GND
VCC
DQ11
DQ10
DQ9
DQ8
NC
A8
A9
A10
A11
NC
123456
A LB OE A0 A1 A2 N.C.
B D8 UB A3 A4 CE D0
„ BLOCK DIAGRAM
A8
A13
A15
A16
A14
A12
A7
A6
A5
A4
DQ0
.
.
.
.
DQ15
Address
Input
Buffer
20
Row
1024
Decoder
Data
16
Input
16
. Buffer
.
. 16
.
Data
Output
16
Buffer
Memory Array
1024 x 2048
2048
Column I/O
Write Driver
Sense Amp
128
Column Decoder
C D9 D10 A5 A6 D1 D2
D
VSS D11 N.C. A7
D3 VCC
E VCC D12 N.C. A16 D4 VSS
CE
WE
OE Control
UB
LB
14
Address Input Buffer
A11 A9 A3 A2 A1 A0 A10
F
D14 D13 A14 A15
D5
D6
G
D15 N.C. A12 A13 WE
D7
Vcc
Gnd
H
N.C. A8
A9 A10 A11 N.C.
Brillian4c8-ebalSl BeGmA toipcvoiewnductor Inc. reserves the right to modify document contents without notice.
R0201-BS616UV2011
1
Revision 2.5
April 2002




BS616UV2011EC pdf, 반도체, 판매, 대치품
BSI
„ LOW VCC DATA RETENTION WAVEFORM ( CE Controlled )
Vcc
CE
Vcc
t CDR
VIH
Data Retention Mode
VDR 1.5V
CE Vcc - 0.2V
BS616UV2011
Vcc
tR
VIH
„ AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0V
5ns
0.5Vcc
„ KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
MUST BE
STEADY
OUTPUTS
MUST BE
STEADY
„ AC TEST LOADS AND WAVEFORMS
2V
OUTPUT
1333
2V
OUTPUT
1333
INCLUDING
JIG AND
SCOPE
100PF
2000
INCLUDING
JIG AND
SCOPE
5PF
2000
FIGURE 1A
FIGURE 1B
OUTPUT
THEVENIN EQUIVALENT
800
1.2V
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
DON , T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
ALL INPUT PULSES
Vcc
GND
10%
90% 90%
←→
FIGURE 2
10%
5ns
„ AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 2.0V )
READ CYCLE
JEDEC
PARAMETER
NAME
t
AVAX
t
AVQV
t
ELQV
t
BA
t
GLQV
t
ELQX
t
BE
t
GLQX
t
EHQZ
t
BDO
t
GHQZ
t
AXOX
PARAMETER
NAME
t
RC
t
AA
t
ACS
t (1)
BA
t
OE
t
CLZ
t
BE
t
OLZ
t
CHZ
t
BDO
t
OHZ
t
OH
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Data Byte Control to Output High Z
Output Disable to Output in High Z
Output Disable to Address Change
(CE)
(LB,UB)
(CE)
(LB,UB)
(CE)
(LB,UB)
BS616UV2011-70
MIN. TYP. MAX.
70 --
--
-- -- 70
-- -- 70
-- -- 35
-- -- 35
10 --
--
10 --
--
10 --
--
0 -- 35
0 -- 35
0 -- 30
10 --
--
BS616UV2011-10
MIN. TYP. MAX.
100 --
--
-- -- 100
-- -- 100
-- -- 50
-- -- 50
15 --
--
15 --
--
15 --
--
0 -- 40
0 -- 40
0 -- 35
15 --
--
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE :
1. tBA is 35ns/50ns (@speed=70ns/100ns) with address toggle. ; .tBA is 70ns/100ns (@speed=70ns/100ns) without address toggle.
R0201-BS616UV2011
4
Revision 2.5
April 2002

4페이지










BS616UV2011EC 전자부품, 판매, 대치품
BSI
WRITE CYCLE2 (1,6)
ADDRESS
CE
LB,UB
WE
D OUT
D IN
BS616UV2011
t WC
t AS
t (11)
CW
(5)
t AW
(4,10)
t WHZ
t BW
t WP
(2)
t DW
t WR
(3)
t DH
(7)
t DH
(8,9)
(8)
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. TWR is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE going low to the end of write.
R0201-BS616UV2011
7
Revision 2.5
April 2002

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BS616UV2011EC

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