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PDF BS62LV1023DI Data sheet ( Hoja de datos )
| Número de pieza | BS62LV1023DI | |
| Descripción | Very Low Power/Voltage CMOS SRAM 128K X 8 bit | |
| Fabricantes | Brilliance Semiconductor | |
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BSI Very Low Power/Voltage CMOS SRAM
128K X 8 bit
BS62LV1023
FEATURES
• Vcc operation voltage : 2.4V ~ 3.6V
• Very low power consumption :
Vcc = 3.0V C-grade : 20mA (Max.) operating current
I- grade : 25mA (Max.) operating current
0.02uA (Typ.) CMOS standby current
• High speed access time :
-70 70ns (Max.) at Vcc = 3.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE2, CE1, and OE options
PRODUCT FAMILY
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
BS62LV1023SC
BS62LV1023TC
BS62LV1023STC
BS62LV1023PC
BS62LV1023JC
BS62LV1023DC
BS62LV1023SI
BS62LV1023TI
BS62LV1023STI
BS62LV1023PI
BS62LV1023JI
BS62LV1023DI
+0 O C to +70 O C
-40 O C to +85 O C
PIN CONFIGURATIONS
2.4V ~ 3.6V
2.4V ~ 3.6V
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1 32
2 31
3 30
4 29
5 28
6 27
7 BS62LV1023SC 26
8 BS62LV1023SI 25
9 BS62LV1023PC 24
10
11
12
BS62LV1023PI
BS62LV1023JC
BS62LV1023JI
23
22
21
13 20
14 19
15 18
16 17
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
BS62LV1023TC
BS62LV1023STC
BS62LV1023TI
BS62LV1023STI
32 OE
31 A10
30 CE1
29 DQ7
28 DQ6
27 DQ5
26 DQ4
25 DQ3
24 GND
23 DQ2
22 DQ1
21 DQ0
20 A0
19 A1
18 A2
17 A3
DESCRIPTION
The BS62LV1023 is a high performance, very low power CMOS
Static Random Access Memory organized as 131,072 words by 8 bits
and operates from a wide range of 2.4V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.02uA and maximum access time of 70ns in 3V operation.
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable (CE2), and active LOW
output enable (OE) and three-state output drivers.
The BS62LV1023 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV1023 is available in DICE form, JEDEC standard 32 pin
450mil Plastic SOP, 300mil Plastic SOJ, 600mil Plastic DIP,
8mmx13.4mm STSOP and 8mmx20mm TSOP.
SPEED
(ns)
Vcc= 3.0V
POWER DISSIPATION
STANDBY
Operating
(ICCSB1, Max)
(ICC, Max)
Vcc=3.0V
Vcc=3.0V
70 1.0uA
20mA
70 1.5uA
25mA
BLOCK DIAGRAM
PKG TYPE
SOP-32
TSOP -32
STSOP -32
PDIP-32
SOJ-32
DICE
SOP-32
TSOP -32
STSOP -32
PDIP-32
SOJ-32
DICE
A6
A7
A12
A14
A16
A15
A13
A8
A9
A11
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CE2
CE1
WE
OE
Vdd
Gnd
Address
Input
Buffer
20
Row
Decoder
1024
Memory Array
1024 x 1024
8
8
Control
Data
Input
Buffer
Data
Output
Buffer
1024
8 Column I/O
Write Driver
Sense Amp
8
128
Column Decoder
14
Address Input Buffer
A5 A4 A3 A2 A1 A0 A10
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS62LV1023
1
Revision 2.2
April 2001
1 page  
BSI
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
ADDRESS
D OUT
t OH
t AA
t RC
BS62LV1023
t OH
READ CYCLE2 (1,3,4)
CE1
t ACS1
CE2
D OUT
READ CYCLE3 (1,4)
ADDRESS
OE
CE1
CE2
D OUT
t ACS2
t (5)
CLZ
t RC
t AA
t OE
t OLZ
t ACS1
t (5)
CLZ1
t ACS2
t (5)
CLZ2
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2= VIH.
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = VIL .
5. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
t t(5)
CHZ1, CHZ2
t OH
t (5)
OHZ
t (1,5)
CHZ1
t (2,5)
CHZ2
R0201-BS62LV1023
5
Revision 2.2
April 2001
5 Page 
BSI
REVISION HISTORY
Revision Description
2.2 2001 Data Sheet release
BS62LV1023
Date
Note
Apr. 15, 2001
R0201-BS62LV1023
11
Revision 2.2
April 2001
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet BS62LV1023DI.PDF ] | |
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