Features
• Single Supply for Read and Write: 2.7V to 3.6 (BV), 3.0 to 3.6V (LV)
• Fast Read Access Time - 70 ns
• Internal Program Control and Timer
• Sector Architecture
– One 16K Byte Boot Block with Programming Lockout
– Two 8K Byte Parameter Blocks
– Two Main Memory Blocks (96K, 128K) Bytes
• Fast Erase Cycle Time - 10 seconds
• Byte By Byte Programming - 30 µs/Byte Typical
• Hardware Data Protection
• DATA Polling For End Of Program Detection
• Low Power Dissipation
– 25 mA Active Current
– 50 µA CMOS Standby Current
• Typical 10,000 Write Cycles
Description
The AT49BV/LV002(N)(T) is a 3-volt-only in-system reprogrammable Flash Memory.
Its 2 megabits of memory is organized as 262,144 words by 8 bits. Manufactured with
Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 70
ns with power dissipation of just 90 mW over the commercial temperature range.
When the device is deselected, the CMOS standby current is less than 50 µA. For the
Pin Configurations
Pin Name
A0 - A17
CE
OE
WE
RESET
I/O0 - I/O7
DC
Function
Addresses
Chip Enable
Output Enable
Write Enable
RESET
Data Inputs/Outputs
Don’t Connect
PLCC Top View
DIP Top View
(continued)
*RESET
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VCC
31 WE
30 A17
29 A14
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
VSOP Top View (8 x 14 mm) or
TSOP Top View (8 x 20 mm)
Type 1
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
5
6
7
8
9
10
11
12
13
29 A14
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 I/O7
A11
A9
A8
A13
A14
A17
WE
VCC
*RESET
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 OE
31 A10
30 CE
29 I/O7
28 I/O6
27 I/O5
26 I/O4
25 I/O3
24 GND
23 I/O2
22 I/O1
21 I/O0
20 A0
19 A1
18 A2
17 A3
*Note: This pin is a DC on the AT49BV002N(T) and AT49LV002N(T).
2-Megabit
(256K x 8)
Single 2.7-Volt
Battery-Voltage™
Flash Memory
AT49BV002
AT49LV002
AT49BV002N
AT49LV002N
AT49BV002T
AT49LV002T
AT49BV002NT
AT49LV002NT
Rev. 0982C–07/98
1
address range of the boot block is 3C000 to 3FFFF for the
AT49BV/LV002(N)T.
Once the feature is enabled, the data in the boot block can
no longer be erased or programmed with input voltage of
5.5V or less. Data in the main memory block can still be
changed through the regular programming method. To acti-
vate the lockout feature, a series of six program commands
to specific addresses with specific data must be performed.
Please refer to the Command Definitions table.
BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the boot
block section is locked out. When the device is in the soft-
ware product identification mode (see Software Product
Identification Entry and Exit sections) a read from address
location 00002H will show if programming the boot block is
locked out for the AT49BV/LV002(N), and a read from
address location 3C002H will show if programming the
bootblock is locked out for AT49BV/LV002(N)T. If the data
on I/O0 is low, the boot block can be programmed; if the
data on I/O0 is high, the program lockout feature has been
activated and the block cannot be programmed. The soft-
ware product identification code should be used to return to
standard operation.
BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE:
The user can override the boot block programming lockout
by taking the RESET pin to 12 volts during the entire chip
erase, sector erase or byte programming operation. When
the RESET pin is brought back to TTL levels the boot block
programming lockout feature is again active. This feature is
not available on the AT49BV/LV002N(T).
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING: The AT49BV/LV002(N)(T) features
DATA polling to indicate the end of a program cycle. During
a program cycle an attempted read of the last byte loaded
will result in the complement of the loaded data on I/O7.
Once the program cycle has been completed, true data is
valid on all outputs and the next cycle may begin. DATA
polling may begin at any time during the program cycle.
TOGGLE BIT: In addition to DATA polling the
AT49BV/LV002(N)(T) provides another method for deter-
mining the end of a program or erase cycle. During a pro-
gram or erase operation, successive attempts to read data
from the device will result in I/O6 toggling between one and
zero. Once the program cycle has completed, I/O6 will stop
toggling and valid data will be read. Examining the toggle
bit may begin at any time during a program cycle.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the
AT49BV/LV002(N)(T) in the following ways: (a) VCC sense:
if VCC is below 1.8V (typical), the program function is inhib-
ited. (b) Program inhibit: holding any one of OE low, CE
high or WE high inhibits program cycles. (c) Noise filter:
pulses of less than 15 ns (typical) on the WE or CE inputs
will not initiate a program cycle.
4 AT49BV/LV002(N)(T)
