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AT49LV1614AT-70CI 데이터시트 PDF




ATMEL Corporation에서 제조한 전자 부품 AT49LV1614AT-70CI은 전자 산업 및 응용 분야에서
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부품번호 AT49LV1614AT-70CI 기능
기능 16-megabit 1M x 16/2M x 8 3-volt Only Flash Memory
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AT49LV1614AT-70CI 데이터시트, 핀배열, 회로
Features
Single Voltage Read/Write Operation: 2.65V to 3.3V (BV), 3.0V to 3.6V (LV)
Access Time – 70 ns
Sector Erase Architecture
– Thirty-one 32K Word (64K Bytes) Sectors with Individual Write Lockout
– Eight 4K Word (8K Bytes) Sectors with Individual Write Lockout
Fast Word Program Time – 20 µs
Fast Sector Erase Time – 300 ms
Dual-plane Organization, Permitting Concurrent Read while Program/Erase
Memory Plane A: Eight 4K Word and Seven 32K Word Sectors
Memory Plane B: Twenty-four 32K Word Sectors
Erase Suspend Capability
– Supports Reading/Programming Data from Any Sector by Suspending Erase of
Any Different Sector
Low-power Operation
– 30 mA Active
– 10 µA Standby
Data Polling, Toggle Bit, Ready/Busy for End of Program Detection
VPP Pin for Accelerated Program/Erase Operations
RESET Input for Device Initialization
Sector Lockdown Support
TSOP and CBGA Package Options
Top or Bottom Boot Block Configuration Available
128-bit Protection Register
Description
The AT49BV/LV16X4A(T) is a 2.65- to 3.3-volt 16-megabit Flash memory organized
as 1,048,576 words of 16 bits each or 2,097,152 bytes of 8 bits each. The x16 data
appears on I/O0 - I/O15; the x8 data appears on I/O0 - I/O7. The memory is divided
into 39 sectors for erase operations. The device is offered in 48-lead TSOP and
48-ball CBGA packages. The device has CE and OE control signals to avoid any bus
contention. This device can be read or reprogrammed using a single 2.65V power
supply, making it ideally suited for in-system programming.
Pin Configurations
Pin Name Function
A0 - A19
Addresses
CE Chip Enable
OE Output Enable
WE Write Enable
RESET
Reset
RDY/BUSY READY/BUSY Output
VPP
Power Supply for Accelerated Program/Erase Operations
I/O0 - I/O14 Data Inputs/Outputs
I/O15 (A-1) I/O15 (Data Input/Output, Word Mode) A-1 (LSB Address Input, Byte Mode)
BYTE
Selects Byte or Word Mode
NC No Connect
VCCQ
Output Power Supply
16-megabit
(1M x 16/2M x 8)
3-volt Only
Flash Memory
AT49BV1604A
AT49BV1604AT
AT49BV1614A
AT49LV1614A
AT49BV1614AT
AT49LV1614AT
Rev. 1411F–FLASH–03/02
1




AT49LV1614AT-70CI pdf, 반도체, 판매, 대치품
Block Diagram
I/O0 - I/O15/A-1
OUTPUT
BUFFER
INPUT
BUFFER
A0 - A19
INPUT
BUFFER
ADDRESS
LATCH
Y-DECODER
X-DECODER
IDENTIFIER
REGISTER
STATUS
REGISTER
DATA
COMPARATOR
Y-GATING
PLANE B
SECTORS
COMMAND
REGISTER
WRITE STATE
MACHINE
PROGRAM/ERASE
VOLTAGE SWITCH
CE
WE
OE
RESET
BYTE
RDY/BUSY
VPP
VCC
GND
PLANE A SECTORS
4 AT49BV1604A(T)/1614A(T)
1411FFLASH03/02

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AT49LV1614AT-70CI 전자부품, 판매, 대치품
1411FFLASH03/02
AT49BV1604A(T)/1614A(T)
128-BIT PROTECTION REGISTER: The AT49BV/LV16X4A(T) contains a 128-bit register that
can be used for security purposes in system design. The protection register is divided into two
64-bit blocks. The two blocks are designated as block A and block B. The data in block A is
non-changeable and is programmed at the factory with a unique number. The data in block B
is programmed by the user and can be locked out such that data in the block cannot be repro-
grammed. To program block B in the protection register, the four-bus cycle Program
Protection Register command must be used as shown in the Command Definition table on
page 8. To lock out block B, the four-bus cycle Lock Protection Register command must be
used as shown in the Command Definition table. Data bit D1 must be zero during the fourth
bus cycle. All other data bits during the fourth bus cycle are dont cares. Please see the Pro-
tection Register Addressing Tableon page 9 for the address locations in the protection
register. To read the protection register, the Product ID Entry command is given followed by a
normal read operation from an address within the protection register. After reading the protec-
tion register, the Product ID Exit command must be given prior to performing any other
operation.
DATA POLLING: The AT49BV/LV16X4A(T) features Data Polling to indicate the end of a pro-
gram cycle. During a program cycle an attempted read of the last byte/word loaded will result
in the complement of the loaded data on I/O7. Once the program cycle has been completed,
true data is valid on all outputs and the next cycle may begin. During a chip or sector erase
operation, an attempt to read the device will give a 0on I/O7. Once the program or erase
cycle has completed, true data will be read from the device. Data Polling may begin at any
time during the program cycle. Please see Status Bit Tableon page 21 for more details.
TOGGLE BIT: In addition to Data Polling, the AT49BV/LV16X4A(T) provides another method
for determining the end of a program or erase cycle. During a program or erase operation,
successive attempts to read data from the same memory plane will result in I/O6 toggling
between one and zero. Once the program cycle has completed, I/O6 will stop toggling and
valid data will be read. Examining the toggle bit may begin at any time during a program cycle.
An additional toggle bit is available on I/O2, which can be used in conjunction with the toggle
bit that is available on I/O6. While a sector is erase suspended, a read or a program operation
from the suspended sector will result in the I/O2 bit toggling. Please see Status Bit Tableon
page 21 for more details.
RDY/BUSY: For the AT49BV/LV1614A(T), an open-drain Ready/Busy output pin provides
another method of detecting the end of a program or erase operation. RDY/BUSY is actively
pulled low during the internal program and erase cycles and is released at the completion of
the cycle. The open-drain connection allows for OR-tying of several devices to the same
RDY/BUSY line.
HARDWARE DATA PROTECTION: The Hardware Data Protection feature protects against
inadvertent programs to the AT49BV/LV16X4A(T) in the following ways: (a) VCC sense: if VCC
is below 1.8V (typical), the program function is inhibited. (b) VCC power-on delay: once VCC
has reached the VCC sense level, the device will automatically time out 10 ms (typical) before
programming. (c) Program inhibit: holding any one of OE low, CE high or WE high inhibits pro-
gram cycles. (d) Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not
initiate a program cycle.
INPUT LEVELS: While operating with a 2.65V to 3.3V power supply, the address inputs and
control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the
operation of the device. The I/O lines can only be driven from 0 to VCC + 0.6V.
OUTPUT LEVELS: For the AT49BV1604A(T), output high levels (VOH) are equal to VCCQ -
0.2V (not VCC). For 2.65V - 3.3V output levels, VCCQ must be tied to VCC. For 1.8V - 2.2V out-
put levels, VCCQ must be regulated to 2.0V ± 10%, while VCC must be regulated to 2.65V - 3.0V
(for minimum power).
7

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부품번호상세설명 및 기능제조사
AT49LV1614AT-70CI

16-megabit 1M x 16/2M x 8 3-volt Only Flash Memory

ATMEL Corporation
ATMEL Corporation

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