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AT49LW080 데이터시트 PDF




ATMEL Corporation에서 제조한 전자 부품 AT49LW080은 전자 산업 및 응용 분야에서
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부품번호 AT49LW080 기능
기능 8-megabit and 4-megabit Firmware Hub Flash Memory
제조업체 ATMEL Corporation
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AT49LW080 데이터시트, 핀배열, 회로
Features
Low Pin Count (LPC) BIOS Device
Functions as Firmware Hub for Intel 810, 810E, 820, 840 Chipsets
8M or 4M Bits of Flash Memory for Platform Code/Data Storage
– Uniform, 64-Kbyte Memory Sectors
– Available in 8M Bits (AT49LW080) and 4M Bits (AT49LW040)
– Automated Byte-program and Sector-erase Operations
Two Configurable Interfaces
– Firmware Hub (FWH) Interface for In-System Operation
– Address/Address Multiplexed (A/A Mux) Interface for Programming during
Manufacturing
Firmware Hub Hardware Interface Mode
– 5-signal Communication Interface Supporting x8 Reads and Writes
– Read and Write Protection for Each Sector Using Software-controlled Registers
– Two Hardware Write-protect Pins: One for the Top Boot Sector, One for All Other
Sectors
– Five General-purpose Inputs, GPIs, for Platform Design Flexibility
– Operates with 33 MHz PCI Clock and 3.3V I/O
Address/Address Multiplexed (A/A Mux) Interface
– 11-pin Multiplexed Address and 8-pin Data Interface
– Supports Fast On-board or Out-of-system Programming
Power Supply Specifications
– VCC: 3.3V ± 0.3V
– VPP: 3.3V and 12V for Fast Programming
Industry-standard Packages
– (40-lead TSOP or 32-lead PLCC)
Description
The AT49LW080 and the AT49LW040 are Flash memory devices designed to be com-
patible with the Intel 82802AC and the Intel 82802AB Firmware Hub (FWH) devices
for PC-Bios Application. A feature of the AT49LW080/040 is the nonvolatile memory
core. The high-performance memory is arranged in eight (AT49LW040) or sixteen
(AT49LW080) 64-Kbyte sectors (see page 13).
Pin Configurations
PLCC
TSOP
[A7] FGPI1
[A6] FGPI0
[A5] WP
[A4] TBL
[A3] ID3
[A2] ID2
[A1] ID1
[A0] ID0
[I/O0] FWH0
5
6
7
8
9
10
11
12
13
29 IC (VIL) [IC(VIH)]
28 GNDa [GNDa]
27 VCCa [VCCa]
26 GND [GND]
25 VCC [VCC]
24 INIT [OE]
23 FWH4 [WE]
22 RFU [RY/BY]
21 RFU [I/O7]
(NC) NC
[IC (VIH)] IC (VIL)
[NC] NC
[NC] NC
[NC] NC
[NC] NC
[A10] FGPI4
[NC] NC
[R/C] CLK
[VCC] VCC
[VPP] VPP
[RST] RST
[NC] NC
[NC] NC
[A9] FGPI3
[A8] FGPI2
[A7] FGPI1
[A6] FGPI0
[A5] WP
[A4] TBL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 GNDa [GNDa]
39 VCCa [VCCa]
38 FWH4 [WE]
37 INIT [OE]
36 RFU [RY/BY]
35 RFU [I/O7]
34 RFU [I/O6]
33 RFU [I/O5]
32 RFU [I/O4]
31 VCC [VCC]
30 GND [GND]
29 GND [GND]
28 FWH3 [I/O3]
27 FWH2 [I/O2]
26 FWH1 [I/O1]
25 FWH0 [I/O0]
24 ID0 [A0]
23 ID1 [A1]
22 ID2 [A2]
21 ID3 [A3]
[ ] Designates A/A Mux Mode
[ ] Designates A/A Mux Mode
8-megabit and
4-megabit
Firmware Hub
Flash Memory
AT49LW080
AT49LW040
Rev. 1966C–FLASH–03/02
1




AT49LW080 pdf, 반도체, 판매, 대치품
Table 1. Pin Description (Continued)
Interface
Symbol
Type
FWH A/A Mux
CLK
INPUT
X
FWH[3:0]
FWH4
ID[3:0]
I/O
INPUT
INPUT
X
X
X
FGPI[4:0]
INPUT
X
TBL
INPUT
X
WP
INPUT
X
A0 - A10
INPUT
X
Name and Function
33 MHz CLOCK for FWH INTERFACE: This input is the same as the PCI
clock and adheres to the PCI specification.
A/A Mux = R/C
FWH I/Os: I/O Communication.
A/A Mux = I/O[3:0]
FWH INPUT: Input Communication.
A/A Mux = WE
IDENTIFICATION INPUTS: These four pins are part of the mechanism
that allows multiple parts to be attached to the same bus. The strapping
of these pins is used to identify the component. The boot device must
have ID[3:0] = 0000 and it is recommended that all subsequent devices
should use a sequential up-count strapping (i.e., 0001, 0010, 0011, etc.).
These pins are pulled down with internal resistors, with values between
20 and 100 kwhen in FWH mode. Any ID pins that are pulled high will
exhibit a leakage current of approximately 200 µA. Any pins intended to
be low may be left to float. In a single FWH system, all may be left
floating.
A/A Mux = A[3:0]
FWH GENERAL PURPOSE INPUTS: These individual inputs can be
used for additional board flexibility. The state of these pins can be read
through FWH registers. These inputs should be at their desired state
before the start of the PCI clock cycle during which the read is attempted,
and should remain at the same level until the end of the read cycle. They
may only be used for 3.3V signals. Unused FGPI pins must not be
floated.
A/A Mux = A[10:6]
TOP SECTOR LOCK: When low, prevents programming or sector erase
to the highest addressable sector (7 in a 4-Mbit, 15 in an 8-Mbit
component) regardless of the state of the lock registers TBL high disables
hardware write protection for the top sector, though register-based
protection still applies. The status of TBL does not affect the status of
sector-locking registers.
A/A Mux = A4
WRITE-PROTECT: When low, prevents programming or sector erase to
all but the highest addressable sectors (0 - 6 in a 4-Mbit, 0 - 14 in an
8-Mbit component), regardless of the state of the corresponding lock
registers. WP-high disables hardware write protection for these sectors,
though register-based protection still applies. The status of TBL does not
affect the status of sector-locking registers.
A/A Mux = A5
LOW-ORDER ADDRESS INPUTS: Inputs for low-order addresses during
read and write operations. Addresses are internally latched during a write
cycle. For the A/A Mux interface these addresses are latched by R/C and
share the same pins as the high-order address inputs.
4 AT49LW080/040
1966C–FLASH–03/02

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AT49LW080 전자부품, 판매, 대치품
AT49LW080/040
CYCLE TYPES: There are two types of cycles that are supported by the
AT49LW080/040: FWH Memory Read and FWH Memory Write. FWH Memory Read or
Write cycles start with a preamble.
PREAMBLE: The preamble consists of a START, IDSEL, 28-bit Address and MSIZE
fields. The preamble is shown in Figure 1. The preamble begins with FWH4 going low
and a START field driven on FWH[3:0]. For FWH Memory Read cycles, the START field
must be 1101b; for FWH Memory Write cycles, the START field must be 1110b. Follow-
ing the START field is the IDSEL field. This field acts like a chip select in that it indicates
which device should respond to the current transaction. The next seven clocks are the
28-bit address, which tell from where to begin reading or writing in the selected device.
Next, an MSIZE value of 0 indicates the master is requesting a single byte.
Figure 1. FWH Memory Cycle Preamble
CLK
FWH4
FWH3 - FWH0
START IDSEL
28-BIT ADDRESS
MSIZE
START: This one-clock field indicates the start of a cycle. It is valid on the last clock that
FWH4 is sampled low. The two start fields that are used for the cycle are shown in Table
3. If the start field that is sampled is not one of these values, then the cycle attempted is
not an FWH memory cycle. It may be a valid memory cycle that the FWH component
may wish to decode, i.e., it may be of the LPC memory cycle variety.
Table 3. Start Fields
FWH[3:0]
1101b
1110b
Indication
FWH Memory Read
FWH Memory Write
IDSEL (DEVICE SELECT): This one-clock field is used to indicate which FWH compo-
nent is being selected. The four bits transmitted over FWH[3:0] during this clock are
compared with values strapped onto pins [ID3:ID0] on the FWH component. If there is a
match, the FWH component will continue to decode the cycle to determine which bytes
are requested on a read or which bytes to update on a write. If there isn’t a match, the
FWH component may discard the rest of the cycle and go into a standby power state.
MADDR (MEMORY ADDRESS): This is a seven-clock field, which gives a 28-bit mem-
ory address. This allows for up to 256 MB per memory device, for a total of a 4 GB
addressable space. The address is transferred with the most significant nibble first.
MSIZE (MEMORY SIZE): “0000b” will be sent in this field. A value of “0000b” corre-
sponds to a single byte transfer.
1966C–FLASH–03/02
7

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