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AT59C11W-10SI-2.7 데이터시트 PDF




ATMEL Corporation에서 제조한 전자 부품 AT59C11W-10SI-2.7은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 AT59C11W-10SI-2.7 기능
기능 4-Wire Serial EEPROMs
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로고 ATMEL Corporation 로고


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AT59C11W-10SI-2.7 데이터시트, 핀배열, 회로
Features
Low Voltage and Standard Voltage Operation
– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
– 2.5 (VCC = 2.5V to 5.5V)
User Selectable Internal Organization
– 1K: 128 x 8 or 64 x 16
– 2K: 256 x 8 or 128 x 16
– 4K: 512 x 8 or 256 x 16
4-Wire Serial Interface
Self-Timed Write Cycle (10 ms max)
High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
– ESD Protection: >4000V
8-Pin PDIP and 8-Pin EIAJ SOIC Packages
Description
The AT59C11/22/13 provides 1024/2048/4096 bits of serial EEPROM (Electrically
Erasable Programmable Read Only Memory) organized as 64/128/256 words of 16
bits each, when the ORG Pin is connected to VCC and 128/256/512 words of 8 bits
each when it is tied to ground. The device is optimized for use in many industrial and
commercial applications where low power and low voltage operation are essential.
The AT59C11/22/13 is available in space saving 8-pin PDIP and 8-pin EIAJ SOIC
packages.
The AT59C11/22/13 is enabled through the Chip Select pin (CS), and accessed via a
4-wire serial interface consisting of Data Input (DI), Data Output (DO), and Clock
(CLK). Upon receiving a READ instruction at DI, the address is decoded and the data
is clocked out serially on the data output pin DO, the WRITE cycle is completely self-
timed and no separate ERASE cycle is required before WRITE. The WRITE cycle is
only enabled when the part is in the ERASE/WRITE ENABLE state. Ready/Busy sta-
tus can be monitored upon completion of a programming operation by polling the
Ready/Busy pin.
The AT59C11/22/13 is available in 5.0V ± 10%, 2.7V to 5.5V and 2.5V to 5.5V ver-
sions.
Pin Configurations
Pin Name
CS
CLK
DI
DO
GND
VCC
ORG
RDY/BUSY
Function
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Power Supply
Internal Organization
Status Output
8-Pin PDIP
8-Pin SOIC
4-Wire Serial
EEPROMs
1K (128 x 8 or 64 x 16)
2K (256 x 8 or 128 x 16)
4K (512 x 8 or 256 x 16)
AT59C11
AT59C22
AT59C13
4-Wire, 1K
Serial E2PROM
Rev. 0173K–07/98
1




AT59C11W-10SI-2.7 pdf, 반도체, 판매, 대치품
AC Characteristics
Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +2.5V to +5.5V,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol
Parameter
Test Condition
Min Typ
4.5V VCC 5.5V
fCLK
CLK Clock Frequency
2.7V VCC 5.5V
2.5V VCC 5.5V
1.8V VCC 5.5V
4.5V VCC 5.5V
tCKH
CLK High Time
2.7V VCC 5.5V
2.5V VCC 5.5V
1.8V VCC 5.5V
4.5V VCC 5.5V
tCKL
CLK Low Time
2.7V VCC 5.5V
2.5V VCC 5.5V
1.8V VCC 5.5V
4.5V VCC 5.5V
tCS
Minimum CS Low Time
2.7V VCC 5.5V
2.5V VCC 5.5V
1.8V VCC 5.5V
4.5V VCC 5.5V
tCSS
CS Setup Time
Relative to SK
2.7V VCC 5.5V
2.5V VCC 5.5V
1.8V VCC 5.5V
4.5V VCC 5.5V
tDIS
DI Setup Time
Relative to SK
2.7V VCC 5.5V
2.5V VCC 5.5V
1.8V VCC 5.5V
tCSH
CS Hold Time
Relative to SK
4.5V VCC 5.5V
tDIH
DI Hold Time
Relative to SK
2.7V VCC 5.5V
2.5V VCC 5.5V
1.8V VCC 5.5V
tPD1
Output Delay to ‘1’
AC Test
4.5V VCC 5.5V
2.7V VCC 5.5V
2.5V VCC 5.5V
1.8V VCC 5.5V
tPD0
Output Delay to ‘0’
AC Test
4.5V VCC 5.5V
2.7V VCC 5.5V
2.5V VCC 5.5V
1.8V VCC 5.5V
tRBD
RDY/BUSY Delay to
Status Valid
AC Test
4.5V VCC 5.5V
2.7V VCC 5.5V
2.5V VCC 5.5V
1.8V VCC 5.5V
tCZ
CS to DO in High
Impedance
AC Test
CS = VIL
4.5V VCC 5.5V
2.7V VCC 5.5V
2.5V VCC 5.5V
1.8V VCC 5.5V
tWC
Endurance(1)
Write Cycle Time
5.0V, 25°C, Page Mode
Note: 1. This paramter is characterized and is not 100% tested.
0
0
0
0
250
250
500
1000
250
250
500
1000
250
250
500
1000
50
50
100
200
100
100
200
400
0
100
100
200
400
0.1
1M
Max
1
1
0.5
0.25
Units
MHz
ns
ns
ns
ns
ns
ns
ns
250
250
500
1000
250
250
500
1000
250
250
500
1000
100
100
200
400
10
ns
ns
ns
ns
ms
Write Cycles
4 AT59C11/22/13

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AT59C11W-10SI-2.7 전자부품, 판매, 대치품
AT59C11/22/13
Functional Description
The AT59C11/22/13 are accessed via a simple and versa-
tile 4-wire serial communication interface. Device operation
is controlled by six instructions issued by the host proces-
sor. A valid instruction starts with a rising edge of CS
and consists of a Start Bit (logic ‘1’) followed by the appro-
priate Op Code and the desired memory Address location.
READ (READ): The Read (READ) instruction contains
the Address code for the memory location to be read. After
the instruction and address are decoded, data from the
selected memory location is available at the serial output
pin DO. Output data changes are synchronized with the ris-
ing edges of serial clock CLK. It should be noted that a
dummy bit (logic ‘0’) precedes the 8- or 16-bit data output
string.
ERASE/WRITE (EWEN): To assure data integrity, the
part automatically goes into the Erase/Write Disable
(EWDS) state when power is first applied. An Erase/Write
Enable (EWEN) instruction must be executed first before
any programming instructions can be carried out. Please
note that once in the Erase/Write Enable state, program-
ming remains enabled until an Erase/Write Disable
(EWDS) instruction is executed or VCC power is removed
from the part.
WRITE (WRITE): The Write (WRITE) instruction contains
the 8 or 16 bits of data to be written into the specified mem-
ory location. The self-timed programming cycle, tWP, starts
Timing Diagrams
Synchronous Data Timing
after the last bit of data is received at serial data input pin
DI. The Ready/Busy status of the AT59C11/22/13 can be
determined by polling the RDY/BUSY pin. A logic ‘0’ at
RDY/BUSY indicates that programming is still in progress.
A logic ‘1’ indicates that the memory location at the speci-
fied address has been written with the data pattern con-
tained in the instruction and the part is ready for further
instructions.
ERASE ALL (ERAL): The Erase All (ERAL) instruction
programs every bit in the memory array to the logic ‘1’ state
and is primarily used for testing purposes. The Ready/Busy
status of the AT59C11/22/13 can be determined by polling
the RDY/BUSY pin. The ERAL instruction is valid only at
VCC = 5.0V ± 10%.
WRITE ALL (WRAL): The Write All (WRAL) instruction
programs all memory locations with the data patterns spec-
ified in the instruction. The Ready/Busy status of the
AT59C11/22/13 can be determined by polling the
RDY/BUSY pin. The WRAL instruction is valid only at VCC =
5.0V ± 10%.
ERASE/WRITE DISABLE (EWDS): To protect against
accidental data disturb, the Erase/Write Disable (EWDS)
instruction disables all programming modes and should be
executed after all programming operations. The operation
of the READ instruction is independent of both the EWEN
and EWDS instructions and can be executed at any time.
Note: 1. This is the minimum CLK period.
7

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