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PDF AT5FC008-20 Data sheet ( Hoja de datos )
| Número de pieza | AT5FC008-20 | |
| Descripción | 8-Megabyte Flash Memory PCMCIA Card | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AT5FC008-20 (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
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Features
• Single Power Supply
Read and Write Voltage, 5 V ± 5%
• High Performance
200 ns Maximum Access Time
6 ms Typical Sector Write
• CMOS Low Power Consumption
25 mA Typical Active Current (Byte Mode)
400 µA Typical Standby Current
• Fully MS-DOS Compatible Flash Driver and Formatter
Virtual-Disk Flash Driver with 512 Bytes/Sector
Random Read/Write to any Sector
No Erase Operation Required Prior to any Write
• Zero Data Retention Power
Batteries not Required for Data Storage
• PCMCIA/JEIDA 68-Pin Standard
Selectable Byte- or Word-Wide Configuration
• High Re-programmable Endurance
Built-in Redundancy for Sector Replacement
Minimum 100,000 Write Cycles
• Five Levels of Write Protection
Prevent Accidental Data Loss
Block Diagram
23
PCMCIA
JEIDA
16
68 PINS
5
ADDRESS
BUFFERS
A1-A19
19
DATA
TRANSCEIVERS
BUS
CONTROL
16
A0,
A20,
A21,
A22
8-MBYTE FLASH
MEMORY ARRAY
CEX, WE, OE, REG
Pin Configuration
Pin Name
A0-A22
D0-D15
CE1, CE2,
WE, OE, REG
CD, WP
BVD1, BVD2
Function
Addresses
Data
Control Signals
Card Status
GND
D3
D4
D5
D6
D7
CE1
A10
OE
A11
A9
A8
A13
A14
WE
NC
VCC
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
WP
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35 GND
36 CD1
37 D11
38 D12
39 D13
40 D14
41 D15
42 CE2
43 NC
44 RFU
45 RFU
46 A17
47 A18
48 A19
49 A20
50 A21
51 VCC
52 NC
53 A22
54 NC
55 NC
56 NC
57 NC
58 NC
59 NC
60 NC
61 REG
62 BVD2
63 BVD1
64 D8
65 D9
66 D10
67 CD2
68 GND
8-Megabyte
Flash Memory
PCMCIA Card
AT5FC008
Preliminary
1 page  
AT5FC008
Pin Description
Symbol
A0-A22
D0-D15
CE1, CE2
OE
WE
VCC
GND
CD1, CD2
WP
NC
BVD1, BVD2
REG
Name
Address Inputs
Data Input/Output
Card Enable
Output Enable
Write Enable
PC Card Power
Supply
Ground
Card Detect
Write Protect
No Connect
Battery Voltage Detect
Register Select
Type
Function
Input
Address Inputs are internally latched during write cycles.
Input/Output
Data Input/Outputs are internally latched on write cycles.
Data outputs are latched during read cycles. Data pins
are active high. When the memory card is de-selected or
the outputs are disabled the outputs float to tri-state.
Input
Card Enable is active low. The memory card is
de-selected and power consumption is reduced to
standby levels when CE is high. CE activates the internal
memory card circuitry that controls the high and low byte
control logic of the card, input buffers, segment decoders,
and associated memory devices.
Input
Output Enable is active low and enables the data buffers
through the card outputs during read cycles.
Input
Write Enable is active low and controls the write function
to the memory array. The target address is latched on the
falling edge of the WE pulse and the appropriate data is
latched on the rising edge of the pulse.
PC Card Power Supply for device operation
(5.0 V ± 5%)
Ground
Output
When Card Detect 1 and 2 = Ground the system detects
the card.
Output
Write Protect is active high and indicates that all card
write operations are disabled by the write protect switch.
Corresponding pin is not connected internally.
Output
Internally pulled up. (There is no battery in the card.)
Input
Provide access to Card Information Structure in the
Attribute Memory Device
5
5 Page 
Write Cycle Characteristics
Symbol
tWC
tAS
tAH
tDS
tDH
tWP
tBLC
tWPH
Parameter
Write Cycle Time
Address Set-up Time
Address Hold Time
Data Set-up Time
Data Hold Time
Write Pulse Width
Byte Load Cycle Time
Write Pulse Width High
Min
10
60
60
10
100
100
AT5FC008
Max Units
10 ms
ns
ns
ns
ns
ns
150 µs
ns
A.C. Write Waveforms (Byte Mode)
OE
CE2
CE1
WE
tAS
A0
A1-A8
A9-A19
DATA
tWP
tAH
BYTE
ADDRESS
SECTOR
ADDRESS
tDS
BYTE 0
BYTE 1
tWPH
tBLC
tDH
BYTE 2
tWC
BYTE 510
BYTE 511
Notes:
1. A20, A21 and A22 specify the pair of AT29C040 devices to be
written, while A0 controls the selection of even and odd bytes.
A0, A20, A21 and A22 must be valid throughout the entire WE
low pulse.
2. A9 through A19 must specify the sector address during each high
to low transition of WE (or CE).
3. OE must be high when WE and CE are both low.
4. All bytes that are not loaded within the sector being pro-
grammed will be erased to FF.
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet AT5FC008-20.PDF ] | |
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