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기능 Coprocessor Field Programmable Gate Arrays
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AT6010LV-4JC 데이터시트, 핀배열, 회로
AT6000/LV Series
Features
High Performance
System Speeds > 100 MHz
Flip-Flop Toggle Rates > 250 MHz
1.2 ns/1.5 ns Input Delay
3.0 ns/6.0 ns Output Delay
Up to 204 User I/Os
Thousands of Registers
•• Cache Logic® Design
Complete/Partial In-System Reconfiguration
No Loss of Data or Machine State
Adaptive Hardware
Low Voltage and Standard Voltage Operation
5.0 (VCC = 4.75V to 5.25V)
3.3 (VCC = 3.0V to 3.6V)
Automatic Component Generators
Reusable Custom Hard Macro Functions
Very Low Power Consumption
Standby Current of 500 µA/ 200 µA
Typical Operating Current of 15 to 170 mA
Programmable Clock Options
Independently Controlled Column Clocks
Independently Controlled Column Resets
Clock Skew Less Than 1 ns Across Chip
Independently Configurable I/O (PCI Compatible)
TTL/CMOS Input Thresholds
Open Collector/Tri-state Outputs
Programmable Slew-Rate Control
I/O Drive of 16 mA (combinable to 64 mA)
Easy Migration to Atmel Gate Arrays for High Volume Production
Description
AT6000 Series SRAM-Based Field Programmable Gate Arrays (FPGAs) are ideal for
use as reconfigurable coprocessors and implementing compute intensive logic.
Supporting system speeds greater than 100 MHz and using a typical operating current
of 15 to 170 mA, AT6000 Series devices are ideal for high-speed, compute-intensive
designs. These FPGAs are designed to implement Cache Logic®, which provides the
user with the ability to implement adaptive hardware and perform hardware accelera-
tion.
The patented AT6000 Series architecture employs a symmetrical grid of small yet
powerful cells connected to a flexible busing network. Independently controlled clocks
and resets govern every column of cells. The array is surrounded by programmable
I/O. (continued)
AT6000 Series Field Programmable Gate Arrays
Device
Usable Gates
Cells
Registers (maximum)
I/O (maximum)
Typ. Operating Current (mA)
Cell Rows x Columns
AT6002
6,000
1,024
1,024
96
15-30
32 x 32
AT6003
9,000
1,600
1,600
120
25-45
40 x 40
AT6005
15,000
3,136
3,136
108
40-80
56 x 56
AT6010
30,000
6,400
6,400
204
85-170
80 x 80
Coprocessor
Field
Programmable
Gate Arrays
AT6000 and AT6000LV Se-
ries
0264E
2-3




AT6010LV-4JC pdf, 반도체, 판매, 대치품
Description (Continued)
the array with read/write access to two North-South and
two East-West buses.
Each cell, in addition, provides the ability to route a signal
on a 90° turn between the NS1 bus and EW1 bus and
between the NS2 bus and EW2 bus.
Express buses are not connected directly to cells, and
thus provide higher speeds. They are the fastest way to
cover long, straight-line distances within the array.
Each express bus is paired with a local bus, so there are
two express buses for every column and two express
buses for every row of cells.
Connective units, called repeaters, spaced every eight
cells, divide each bus, both local and express, into seg-
ments spanning eight cells. Repeaters are aligned in rows
and columns thereby partitioning the array into 8 x 8 sec-
tors of cells. Each repeater is associated with a local/ex-
press pair, and on each side of the repeater are connec-
tions to a local-bus segment and an express-bus segment.
The repeater can be programmed to provide any one of
twenty-one connecting functions. These functions are
symmetric with respect to both the two repeater sides and
the two types of buses.
Among the functions provided are the ability to:
Isolate bus segments from one another
Connect two local-bus segments
Connect two express-bus segments
Implement a local/express transfer
In all of these cases, each connection provides signal re-
generation and is thus unidirectional. For bidirectional
connections, the basic repeater function for the NS2 and
EW2 repeaters is augmented with a special programma-
ble connection allowing bidirectional communication be-
tween local-bus segments. This option is primarily used to
implement long, tri-state buses.
Figure 4. Cell Structure
2-6 AT6000/LV Series
The Cell Structure
The Atmel cell (Figure 4) is simple and small and yet can
be programmed to perform all the logic and wiring func-
tions needed to implement any digital circuit. Its four sides
are functionally identical, so each cell is completely sym-
metrical.
Read/write access to the four local buses— NS1, EW1,
NS2 and EW2— is controlled, in part, by four bidirectional
pass gates connected directly to the buses. To read a lo-
cal bus, the pass gate for that bus is turned on and the
three-input multiplexer is set accordingly. To write to a lo-
cal bus, the pass gate for that bus and the pass gate for
the associated tri-state driver are both turned on. The two-
input multiplexer supplying the control signal to the drivers
permits either: (1) active drive, or (2) dynamic tri-stating
controlled by the B input. Turning between LNS1 and LEW1
or between LNS2 and LEW2 is accomplished by turning on
the two associated pass gates. The operations of reading,
writing and turning are subject to the restriction that each
bus can be involved in no more than a single operation.
In addition to the four local-bus connections, a cell re-
ceives two inputs and provides two outputs to each of its
North (N), South (S), East (E) and West (W) neighbors.
These inputs and outputs are divided into two classes: “A”
and “B.” There is an A input and a B input from each neigh-
boring cell and an A output and a B output driving all four
neighbors. Between cells, an A output is always con-
nected to an A input and a B output to a B input.
Within the cell, the four A inputs and the four B inputs enter
two separate, independently configurable multiplexers.
Cell flexibility is enhanced by allowing each multiplexer to
select also the logical constant “1.” The two multiplexer
outputs enter the two upstream AND gates.
Downstream from these two AND gates are an Exclusive-
OR (XOR) gate, a register, an AND gate, an inverter and
two four-input multiplexers producing the A and B outputs.
These multiplexers are controlled in tandem (unlike the A
and B input multiplexers) and determine the function of the
cell.
In State 0— corresponding to the “0" inputs of the mul-
tiplexers— the output of the left-hand upstream AND
gate is connected to the cell’s A output, and the output
of the right-hand upstream AND gate is connected to
the cell’s B output.
In State 1— corresponding to the “1" inputs of the mul-
tiplexers— the output of the left-hand upstream AND
gate is connected to the cell’s B output, the output of the
right-hand upstream AND gate is connected to the cell’s
A output.
In State 2— corresponding to the “2" inputs of the mul-
tiplexers— the XOR of the outputs from the two up-
stream AND gates is provided to the cell’s A output,
(continued)

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AT6010LV-4JC 전자부품, 판매, 대치품
AT6000/LV Series
Description (Continued)
Input/Output
The Atmel architecture provides a flexible interface be-
tween the logic array, the configuration control logic and
the I/O pins.
Two adjacent cells— an “exit” and an “entrance” cell— on
the perimeter of the logic array are associated with each
I/O pin.
There are two types of I/Os: A-type (Figure 8a) and B-type
(Figure 8b). For A-type I/Os, the edge-facing A output of
an exit cell is connected to an output driver, and the edge-
facing A input of the adjacent entrance cell is connected to
an input buffer. The output of the output driver and the
input of the input buffer are connected to a common pin.
B-type I/Os are the same as A-type I/Os, but use the B
inputs and outputs of their respective entrance and exit
cells. A- and B-type I/Os alternate around the array.
Control of the I/O logic is provided by user-configurable
memory bits.
TTL/CMOS Inputs
A user-configurable bit determines the threshold level—
TTL or CMOS— of the input buffer.
Open Collector/Tri-state Outputs
A user-configurable bit which enables or disables the ac-
tive pull-up of the output device.
Slew Rate Control
A user-configurable bit controls the slew rate— fast or
slow— of the output buffer. A slow slew rate, which re-
duces noise and ground bounce, is recommended for out-
puts that are not speed-critical. Fast and slow slew rates
have the same DC-current sinking capabilities, but the
rate at which each allows the output devices to reach full
drive differs.
Pull-up
A user-configurable bit controls the pull-up transistor in the
I/O pin. It’s primary function is to provide a logical “1" to
unused input pins. When on, it is approximately equivalent
to a 25K resistor to VCC.
Enable Select
User-configurable bits determine the output-enable for the
output driver. The output driver can be static - - always on
or always off - - or dynamically controlled by a signal gen-
erated in the array. Four options are available from the
array: (1) the control is low and always driving; (2) the con-
trol is high and never driving; (3) the control is connected
to a vertical local bus associated with the output cell; or (4)
the control is connected to a horizontal local bus associ-
ated with the output cell. On power-up, the user I/Os are
configured as inputs with pull-up resistors.
In addition to the functionality provided by the I/O logic, the
entrance and exit cells provide the ability to register both
inputs and outputs. Also, these perimeter cells (unlike in-
terior cells) are connected directly to express buses: the
edge-facing A and B outputs of the entrance cell are con-
nected to express buses, as are the edge-facing A and B
inputs of the exit cell. These buses are perpendicular to
the edge, and provide a rapid means of bringing I/O sig-
nals to and from the array interior and the opposite edge
of the chip.
Figure 8a. A-Type I/O Logic
Figure 8b. B-Type I/O Logic
2-9

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부품번호상세설명 및 기능제조사
AT6010LV-4JC

Coprocessor Field Programmable Gate Arrays

ATMEL Corporation
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