|
|
PDF AT76C101 Data sheet ( Hoja de datos )
| Número de pieza | AT76C101 | |
| Descripción | JPEG Image Compression Processor | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AT76C101 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
|
No Preview Available !
Features
• Compatible with the JPEG Baseline Standard as Defined by ISO IS 109 18-1
• Highly-integrated, Low-cost Single Chip Solution
• Up to 40 Mbytes/sec Sustained Compression Rate
• Maximum Processing Rate of 1.6 million pixels/sec
• Supports 8-bit Grayscale and YUV 4:2:2 Color Space Input and Output Formats
• Handles Images of Size up to 1024 x 1024 Pixels
• Fast DCT/IDCT Processor On-chip
• User-defined Quantization and Huffman Tables
• Support for Fast as well as Slow/Inexpensive Memories
• Provides Direct Interface for Microcontroller/Microprocessor Access
Applications
The AT76C101 JPEG Processor is optimized for use in the following applications:
• Digital Cameras
• Color Printers and Plotters
• Low-cost Image Compression Systems
• Video Editing (3-4 frames/sec at CCIR 720 x 480 Image Resolution)
Hardware Resources
• On-chip Video Interface
• Custom Discrete Cosine Transform and Quantization Processor
• Variable Length and Huffman Encoder/Decoder
• Programmable Memory Interface (Supports Slow Memories)
• Microcontroller/Microprocessor Access Bus
Pin Configuration
100-Pin QFP
SRDATA15-0
SRADDR14-0
PXWE
PXRE
PXIN
PXOUT
STOP_PIXEL
SRDRIVE
H_SYNC
V_SYNC
PX_CLK
CLK_IN
M_ADDR19-0
M_DATA7-0
MEM_CS
TEST
RESET
FRAMEND
FREEZE
MASTER_CS
MASTER_WR
MASTER_OE
BUSY
BST_TEST
JPEG Image
Compression
Processor
AT76C101
Rev. 0751A–04/98
1
1 page  
AT76C101
Compressed Data Memory Management
The AT76C101 starts reading/writing data from/to the com-
pressed data memory starting from the address location
specified by the Mem_Start_Addr register. Once a frame
has been processed, the AT76C101 writes the address of
the last compressed data into the Mem_End_Addr register.
The microcontroller uses this information to keep track of
the memory locations having valid images, and to specify
the starting memory address of the next image
Initialization Sequence
The active high RESET signal resets all the AT76C101
resources including the register file. Once the AT76C101
has been reset, the microcontroller can program the chip to
the desired mode of operation. The microcontroller will also
have to load the internal Huffman and Quantization Tables.
Once the internal registers and tables have been initialized,
the microcontroller can initiate a compression/decompres-
sion operation by asserting the Start_Reg register. The
AT76C101 de-asserts this signal after the final image block
is processed. When the AT76C101 completes the process-
ing of an image, it asserts the FRAMEND signal, writes the
address of the last compressed data into the
Mem_End_Addr register and waits for a new Start_Reg
request.
During decompression, the microcontroller has to do some
additional processing of the JPEG data stream. The micro-
controller extracts and process the JPEG header informa-
tion from the compressed data stream. Based on this
header information, the microcontroller then initializes the
internal registers of the AT76C101 and writes the address
of the memory location containing the first compressed
image data (not the start of the JPEG header) into the
Mem_Start_Addr register. It then follows the above men-
tioned initialization sequence.
Quantization Table Loading
The on-chip quantization tables must be loaded with the
required values before the normal operation of the chip.
The AT76C101’s quantization table is a 256x16 RAM, and
can store up to four 64-word quantization tables. The upper
half of the RAM area is used to store the compression
quantization tables and the lower half to store the decom-
pression tables. The organization of the quantization RAM
is shown in Figure 4. The Quantization Tables can be
loaded only after the Quant_Table_Load_Enable register
has been set. Once loaded, the quantization tables remain
valid until the power is switched off or until they are repro-
grammed (they are unaffected by RESET). The
Quant_Table_Load_Enable register has to be reset after
the tables are loaded and before normal operation of the
chip can begin.
Figure 4. Internal Memory Organization (Quantization and MaxMin Tables)
0000h
0002h
0000h
0001h
QUANTIZATION VALUE (BITS 7-0)
QUANTIZATION VALUE (BITS 15-8)
0080h
Y
ENCODING
UV
QUANTIZATION VALUE
16 BITS
0100h
0180h
Y
DECODING
UV
QUANTIZATION TABLE
3000h
3008h
3080h
3100h
3180h
DC-Y
DC-UV
AC-Y
AC-UV
3000h
3001h
3002h
3003h
3004h
3005h
3006h
3007h
MAXMIN TABLE
MIN_CODE (BITS 7-0)
MIN_CODE (BITS 15-8)
MAX_CODE (BITS 7-0)
MAX_CODE (BITS 15-8)
VAL_PTR
NOT USED
40 BITS
VAL_PTR MAX_CODE MIN_CODE
8 BITS
16 BITS
16 BITS
5
5 Page 
AT76C101
Table 2. Register File Description
Register
Address
FIFO_Status
0F817
Write_Cnt_Reg
0F818
Read_Cnt_Reg
0F819
Mem_Start_Addr_Low
0F81A
Mem_Start_Addr_Med
Mem_Start_Addr_High
Mem_End_Addr_Low
0F81B
0F81C
0F81D
Mem_End_Addr_Med
Mem_End_Addr_High
0F81E
0F81F
R/W Description
R Shows the status of the internal FIFO. Bit 0 is the FIFO full indicator and bit 1 is
the FIFO empty indicator.
R/W The number of wait states required during a write to external memory is
programmed into this register.
R/W The number of wait states required during a read from external memory is
programmed into this register.
R/W Mem_Start_Addr - low byte. The external memory start address is
programmed here.
R/W Mem_Start_Adrr - middle byte (bit 16 to 31)
R/W Mem_Start_Addr - high byte (bit 32 to 39)
R Mem_End_Addr - low byte. AT76C101 writes the address of the last byte of the
frame written into the external memory.
R Mem_End_Addr - middle byte (bit 16 to 31).
R Mem_End_Addr - high byte (bit 32 to 39).
Table 3. Internal Memory Addressing
Module
Quantization Tables (256 x 16 bits)
DC Huffman Tables (32 x 28 bits)
AC Huffman Tables (512 x 28 bits)
Maxmin Tables - For Decoding only (64 x 40 bits)
Pixel Buffer (4 buffers of size 128 x 8 bits each)
DCT Coefficient Buffer (2 buffers of size 64 x 16 each)
Compressed Data FIFO (64 x 8 bits)
Address Range
0x00000-0x001FF
0x01000-0x0107F
0x03000-0x031FF
0x04000-0x04200
0x04000-0x04200
0x05000-0x050FF
Write Port 0x06000-0x06040
Read Port 0x07000-0x07040
11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet AT76C101.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AT76C101 | JPEG Image Compression Processor | ATMEL Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |