PDF AT76C551 Data sheet ( Hoja de datos )

Número de pieza	AT76C551
Descripción	Single Chip Bluetooth Controller
Fabricantes	ATMEL Corporation
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Features • Implements Bluetooth™ Specification on Short Distance Wireless Communication in 2.4 GHz ISM Band • Provides 1 Mbps Aggregate Bit Rate • Supports Frequency Hopping Spread Spectrum Physical-layer Interface to Dedicated Transceiver with Frequency Hopping Algorithm Implemented in Hardware • Provides Baseband Functions in Hardware which Implement Bluetooth Low-level Bit Processing Such as Forward Error Correction (FEC), Header Error Check (HEC) and CRC Generation/Checking and Encryption/Decryption • Integrated ARM7TDMI® RISC Processor • Glueless SRAM Interface, Supporting Up to 256K Bytes of Memory • Glueless Flash Memory Interface, Supporting Up to 256K Bytes of Nonvolatile Memory • Glueless PCMCIA Bus Interface Conforming to PC Card Standard – Feb. 1995 • USB Interface Conforming to Universal Serial Bus Standard Version 1.1 • 16550 UART Core Offering 32-byte Receive FIFO and Programmable Baud Rate • Programmable 8/16-bit Wide External Memory Interface • Supports Multiple Reference Clock Frequencies (13.000, 14.400, 16.800, 19.440 MHz) • 176-lead LQFP • 3.3V Supply System Level Block Diagram Receive Data Front-end PCMCIA USB Interface Slave UART Single Chip Bluetooth™ Controller AT76C551 Receive Data Processing Transmit Data Processing 3-Wire Control Bus Clock Generator RSSI Receive Sequencing Manager Internal RAM Memory Interface AMBA Bus Interface Voice CODEC ARM Power Management Rev. 1612D–08/01 1 1 page AT76C551 Pinout and Package Options The AT76C551 controller will be available in three different packages, each will have the same basic functionality but with a different system interface (PCMCIA 8-bit, full-speed USB, extended speed RS-232). The prototype version comes in a LQFP-176 package and supports the three different interfaces simultaneously. Pinout of the Prototype Version VCC 1 EXT_13_MHz 2 EX3T-13-MHz_OUT 4 GND 5 EXT_OSC 6 GND 7 TC_ENABL 8 TC_DATA 9 TC_CLK 10 VCC 11 TC_TXON 12 TXPIN 13 TC_PUPLL 14 TC_PURXTX 15 TC_PUVCO 16 TC_I_CP_SW 17 TC_PUREG 18 TC_RXON 19 TC_LD 20 GND 21 CLK_RXPIN 22 VCC 23 RXPIN 24 RXMODE 25 RXF_PD 26 RXF_CLK 27 28 RXF_OE_ 29 RXF-D7 30 RXF-D6 31 RXF_D5 32 RXF_D4 33 RXF_D3 34 GND 35 RXF_D2 36 RXF_D1 37 RXF_D0 38 VDDAC 39 AGND 40 RSSI 41 AVCC 42 VC_IN 43 AGND 44 VC_OUT AVCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Pin 1 is marked for orientation NCx = No Connection 132 PC_A1 131 PC_A2 130 PC_A3 129 PC_A4 128 PC_A5 127 PC_A6 126 PC_A7 125 VCC 124 PC_A8 123 PC_A9 122 PC_A10 121 PC_A11 120 PC_A12 119 PC_A13 118 PC_A14 117 P_OR_UN 116 GND 115 DM 114 DP 113 VCC 112 U_CD_ 111 USART_RX 110 U_DSR_ 109 GND 108 U_CTS_ 107 U_RI_ 106 USART_TX 105 U_DTR_ 104 U_RTS_ 103 MA0 102 MA1 101 MA2 100 MA3 99 MA4 98 MA5 97 MA6 96 VCC 95 GND 94 MA7 93 MA8 92 MA9 91 MA10 90 MA11 89 MA12 132 PC_A1 131 PC_A2 130 PC_A3 129 PC_A4 128 PC_A5 127 PC_A6 126 PC_A7 125 VCC 124 PC_A8 123 PC_A9 122 PC_A10 121 PC_A11 120 PC_A12 119 PC_A13 118 PC_A14 117 P_OR_UN 116 GND 115 DM 114 DP 113 VCC 112 U_CD_ 111 USART_RX 110 U_DSR_ 109 GND 108 U_CTS_ 107 U_RI_ 106 USART_TX 105 U_DTR_ 104 U_RTS_ 103 MA0 102 MA1 101 MA2 100 MA3 99 MA4 98 MA5 97 MA6 96 VCC 95 GND 94 MA7 93 MA8 92 MA9 91 MA10 90 MA11 89 MA12 1612D–08/01 5 5 Page AT76C551 Signal Description – Pin Name Order (Continued) I = Input, O = Output, B = Bidirectional, Analog I = Analog Input, Analog O = Analog Output Pin Name Type Description Baseband Interface Pins TC_CLK O Clock output for transceiver control bus TC_DATA O Data output for transceiver control bus TC_ENBL O Enable output for transceiver control bus TC_LD I Lock detect input TC_PU_REG O Transceiver voltage regulator power up TC_PU_PLL O Power up output for transceiver PLL TC_PU_VCO O VCO power up output TC_PU_RXTX O Power up output for Transmit/Receive sections of transceiver TC_RX_ON O RX section power up control output TC_TX_ON O TX section power up control output TC_I_CP_SW O Transceiver Current Pump external switch signal RSSI I Receive signal strength indicator input from transceiver TXPIN O Transmit data output to transceiver RXPIN I Receive data input from transceiver CLK_RXPIN I Clock driven to internal RxFront module RX_MODE I If “0”, internal clock recovery enabled and data extracted from external A/D. If “1” only BT packet processing carried out. Clock generation and recovery must be carried out externally RXF_PD O Power Down signal for external A/D RXF_CLK O Clock driven to external A/D RXF_OE_ O Output enable signal for external A/D RXF_D[7:0] I A/D RXF_D[7:0] output bus PCMCIA Interface Pins PC_A[14:0] I Address Bus – Signals A0 through A14 are address-bus input lines. Signal A0 is always used since the data interface is 8 bits wide. PC_D[7:0] B Data Bus – Signals D7 through D0 are the bi-directional data bus for PCMCIA. The most significant bit is D7. NWE I Write Enable – Used to strobe memory write data into the chip from the PCMCIA data bus. Should be deasserted during memory read cycles. It is used for both Common memory and Attribute memory accesses. NOE I Output Enable – Active low output enable signal. It is used to gate memory read data from the BT device onto PCMCIA data bus. It is used for Common memory accesses and Attribute memory Accesses. NCE1 I Card Enable – Used to enable even-numbered word address bytes. A0 is used to select between the even and odd number bytes within the addressed word 1612D–08/01 11 11 Page

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