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AT80F52-16AI 데이터시트 PDF




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부품번호 AT80F52-16AI 기능
기능 8-Bit Microcontroller with 8K Bytes QuickFlash Memory
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AT80F52-16AI 데이터시트, 핀배열, 회로
Features
Compatible with MCS-51™ Products
8K Bytes of Factory Programmable QuickFlashMemory
Fully Static Operation: 0 Hz to 20 MHz
Three-Level Program Memory Lock
256 x 8-Bit Internal RAM
32 Programmable I/O Lines
Three 16-Bit Timer/Counters
Eight Interrupt Sources
Programmable Serial Channel
Low Power Idle and Power Down Modes
8-Bit
Description
The AT80F52 is a low-power, high-performance CMOS 8-bit microcomputer with 8K
bytes of QuickFlash memory. The device is manufactured using Atmel’s high density
nonvolatile memory technology and is compatible with the industry standard 80C51
and 80C52 instruction set and pinout. The on-chip QuickFlash allows custom codes to
be quickly programmed in the factory. By combining a versatile 8-bit CPU with Quick-
Flash on a monolithic chip, the Atmel AT80F52 is a powerful microcomputer which
provides a highly flexible and cost effective solution to many embedded control appli-
cations.
(continued)
Microcontroller
with 8K Bytes
QuickFlash
Memory
AT80F52
Pin Configurations
TQFP
INDEX
CORNER
P1.5
P1.6
P1.7
RST
(RXD) P3.0
NC
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
4 44 34 24 14 03 93 83 73 63 53 4
1 33
2 32
3 31
4 30
5 29
6 28
7 27
8 26
9 25
10 24
11 23
1
21
31
41
51
61
71
1
8
9
2
0
2
12
2
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA
NC
ALE
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
PDIP
(T2) P1.0
(T2 EX) P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
(RXD) P3.0
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
(WR) P3.6
(RD) P3.7
X TA L 2
X TA L 1
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VCC
39 P0.0 (AD0)
38 P0.1 (AD1)
37 P0.2 (AD2)
36 P0.3 (AD3)
35 P0.4 (AD4)
34 P0.5 (AD5)
33 P0.6 (AD6)
32 P0.7 (AD7)
31 EA
30 ALE
29 PSEN
28 P2.7 (A15)
27 P2.6 (A14)
26 P2.5 (A13)
25 P2.4 (A12)
24 P2.3 (A11)
23 P2.2 (A10)
22 P2.1 (A9)
21 P2.0 (A8)
PLCC
INDEX
CORNER
(RXD)
(TXD)
(INT0)
(INT1)
(T0)
(T1)
P1.5
P1.6
P1.7
RST
P3.0
NC
P3.1
P3.2
P3.3
P3.4
P3.5
6 4 2 44 42 40
75 3
1 4 3 4 13 9
8 38
9 37
10 36
11 35
12 34
13 33
14 32
15 31
16 30
11781 92 02 12 22 32 42 52 62 72289
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA
NC
ALE
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
0980A-A–12/97
3-15




AT80F52-16AI pdf, 반도체, 판매, 대치품
If desired, ALE operation can be disabled by setting bit 0 of
SFR location 8EH. With the bit set, ALE is active only dur-
ing a MOVX or MOVC instruction. Otherwise, the pin is
weakly pulled high. Setting the ALE-disable bit has no
effect if the microcontroller is in external execution mode.
PSEN
Program Store Enable is the read strobe to external pro-
gram memory.
When the AT80F52 is executing code from external pro-
gram memory, PSEN is activated twice each machine
cycle, except that two PSEN activations are skipped during
each access to external data memory.
EA
External Access Enable. EA must be strapped to GND in
order to enable the device to fetch code from external pro-
gram memory locations starting at 0000H up to FFFFH.
Note, however, that if lock bit 1 is programmed, EA will be
internally latched on reset.
EA should be strapped to VCC for internal program execu-
tions.
XTAL1
Input to the inverting oscillator amplifier and input to the
internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
Table 1. AT80F52 SFR Map and Reset Values
0F8H
0F0H
B
00000000
0E8H
0E0H
ACC
00000000
0D8H
0D0H
0C8H
PSW
00000000
T2CON
00000000
T2MOD
XXXXXX00
RCAP2L
00000000
0C0H
0B8H
0B0H
0A8H
0A0H
98H
90H
88H
80H
IP
XX000000
P3
11111111
IE
0X000000
P2
11111111
SCON
00000000
P1
11111111
TCON
00000000
P0
11111111
SBUF
XXXXXXXX
TMOD
00000000
SP
00000111
TL0
00000000
DPL
00000000
RCAP2H
00000000
TL1
00000000
DPH
00000000
TL2
00000000
TH0
00000000
TH2
00000000
TH1
00000000
0FFH
0F7H
0EFH
0E7H
0DFH
0D7H
0CFH
0C7H
0BFH
0B7H
0AFH
0A7H
9FH
97H
8FH
PCON
0XXX0000
87H
3-18 AT80F52

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AT80F52-16AI 전자부품, 판매, 대치품
AT80F52
Figure 2 shows Timer 2 automatically counting up when
DCEN = 0. In this mode, two options are selected by bit
EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to
0FFFFH and then sets the TF2 bit upon overflow. The over-
flow also causes the timer registers to be reloaded with the
16-bit value in RCAP2H and RCAP2L. The values in Timer
in Capture ModeRCAP2H and RCAP2L are preset by soft-
ware. If EXEN2 = 1, a 16-bit reload can be triggered either
by an overflow or by a 1-to-0 transition at external input
T2EX. This transition also sets the EXF2 bit. Both the TF2
and EXF2 bits can generate an interrupt if enabled.
Setting the DCEN bit enables Timer 2 to count up or down,
as shown in Figure 3. In this mode, the T2EX pin controls
Figure 2. Timer 2 Auto Reload Mode (DCEN = 0)
the direction of the count. A logic 1 at T2EX makes Timer 2
count up. The timer will overflow at 0FFFFH and set the
TF2 bit. This overflow also causes the 16-bit value in
RCAP2H and RCAP2L to be reloaded into the timer regis-
ters, TH2 and TL2, respectively.
A logic 0 at T2EX makes Timer 2 count down. The timer
underflows when TH2 and TL2 equal the values stored in
RCAP2H and RCAP2L. The underflow sets the TF2 bit and
causes 0FFFFH to be reloaded into the timer registers.
The EXF2 bit toggles whenever Timer 2 overflows or
underflows and can be used as a 17th bit of resolution. In
this operating mode, EXF2 does not flag an interrupt.
OSC
÷12
T2 PIN
C/T2 = 0
C/T2 = 1
CONTROL
TR2
RELOAD
TH2 TL2
RCAP2H RCAP2L
OVERFLOW
TIMER 2
INTERRUPT
T2EX PIN
TRANSITION
DETECTOR
TF2
EXF2
CONTROL
EXEN2
Table 4. T2MOD—Timer 2 Mode Control Register
T2MOD Address = 0C9H
Reset Value = XXXX XX00B
Not Bit Addressable
T2OE
DCEN
Bit 7 6 5 4 3 2 1 0
Symbol
T2OE
DCEN
Function
Not implemented, reserved for future
Timer 2 Output Enable bit.
When set, this bit allows Timer 2 to be configured as an up/down counter.
3-21

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