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PDF AT83C24-TISUM Data sheet ( Hoja de datos )
| Número de pieza | AT83C24-TISUM | |
| Descripción | Smart Card Reader Interface with Power Management | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Smart Card Interface
– Compliance with ISO 7816, EMV2000, GIE-CB, GSM and WHQL Standards
Card Clock Stop High or Low for Card Power-down Modes
Support Synchronous Cards with C4 and C8 Contacts
Card Detection and Automatic de-activation Sequence
Programmable Activation Sequence
– Direct Connection to the Smart Card
Logic Level Shifters
Short Circuit Current Limitation (see electrical characteristics)
8kV+ ESD Protection (MIL/STD 883 Class 3)
– Programmable Voltage
5V ±5% at 65 mA (Class A)
3V ±0.2V at 65 mA (Class B)
1.8V ±0.14V at 40 mA
– Low Ripple Noise: < 200 mV
• Versatile Host Interface
– ICAM (Conditional Access) Compatible
– Two Wire Interface (TWI) Link
Programmable Address Allow up to 8 Devices
– Programmable Interrupt Output
– Automatic Level Shifter (1.6V to VCC)
• Reset Output Includes
– Power-On Reset (POR)
– Power-Fail Detector (PFD)
• High-efficiency Step-up Converter: 80 to 98% Efficiency
• Extended Voltage Operation: 3V to 5.5V
• Low Power Consumption
– 180 mA Maximum In-rush Current
– 30 µA Typical Power-down Current (without Smart Card)
• 4 to 48 MHz Clock Input, 7 MHz Min for Step-up Converter (for AT83C24)
• 18 to 48MHz Clock input (for AT83C24NDS)
• Industrial Temperature Range: -40 to +85°C
• Packages: SO28 and QFN28
Smart Card
Reader
Interface with
Power
Management
AT83C24
AT83C24NDS
Description
The AT83C24 is a smart card reader interface IC for smart card reader/writer applica-
tions such as EFT/POS terminals and set top boxes. It enables the management of
any type of smart card from any kind of host. Up to 8 AT83C24 can be connected in
parallel using the programmable TWI address.
Its high efficiency DC/DC converter, low quiescent current in standby mode makes it
particularly suited to low power and portable applications. The reduced bill of material
allows reducing significantly the system cost. A sophisticated protection system guar-
antees timely and controlled shutdown upon error conditions.
The AT83C24NDS is a dedicated version approved by NDS for use with NDS Video-
Guard conditional access software in set-top boxes. All AT83C24 datasheet is
applicable to AT83C24NDS. The main differences between AT83C24 and
AT83C24NDS are listed below:
1/ CLASS A card supplied with CVCC = 4.75 to 5.25V for AT83C24NDS,
CLASS A card supplied with CVCC = 4.6 to 5.25V for AT83C24
2/ 18MHz minimum on input clock for AT83C24NDS
3/ Up to 10µF for capacitor connected on CVCC pin for AT83C24,
3.3µF mandatory for AT83C24NDS
4234E–SCR–09/04
1
1 page  
AT83C24
Table 1. Ports Description (Continued)
Pad Name
Pad Internal
Power Supply
ESD
Limits
Pad
Type Description
CVCC
8 kV+
PWR
Card Supply Voltage
CVCC is the programmable voltage output for the Card interface.
It must be connected to external decoupling capacitors (see page 35 and page 36).
CVCCin
8 kV+
Card Supply Voltage
PWR
This pin must be connected to CVCC.
DVCC
3 kV+
PWR
Digital Supply Voltage
Is internally generated and used to supply the digital core.
This pin has to be connected to an external capacitor of 100 nF and should not be
connected to other devices.
EVCC
3 kV+
PWR
Extra Supply Voltage (Microcontroller power supply)
EVCC is used to supply the internal level shifters of host interface pins.
EVCC voltage can be supplied from the external EVCC pin connected to the host power
supply.
If EVCC cannot be connected to the host power supply, it must be tied to an external
capacitor. EVCC voltage can be generated internally by an automatic follow up of the
logic high level on the I/O pin. In this configuration, connect a 100 nF + 100kOhms in
parallel between EVCC pin and VSS pin.
CVSS
8 kV+
DC/DC Ground
GND
CVSS is used to sink high shunt currents from the external coil.
VSS
GND Ground
Note:
ESD Test conditions: 3 positive and 3 negative pulses on each pin versus GND. Pulses
generated according to Mil/STD 883 Class3. Recommended capacitors soldered on
CVCC and VCC pins.
4234E–SCR–09/04
5
5 Page 
AT83C24
CIO, CC4, CC8 Controller
The CIO, CC4, CC8 output pins are driven respectively by CARDIO, CARDC4,
CARDC8 bits values or by I/O, C4, C8 signal pins. This selection depends of the IODIS
bit value. If IODIS is reset, data are bidirectional between respectively I/O, C4, C8 pins
and CIO, CC4, CC8 pins.
Figure 5. CIO, CC4, CC8 Block Diagram
I/O
EVCC CARDIO bit
C4
EVCC CARDC4 bit
C8
CARDC8 bit
0
1
0
1
0
1
CVCC
CIO
CVCC
CC4
CVCC
CC8
IODIS bit
Clock Controller
IO and CIO pins are linked together through the on chip level shifters if IODIS bit=0 in
INTERFACE register. This is done automatically during an hardware activation.
Their iddle level are 1. With IO high, CIO is pulled up.
The same behavior is applicable on C4/ CC4 and C8/ CC8 pins.
The maximum frequency on those lines depends on CLK frequency (3 clock rising
edges to transfer). With CLK=27MHz, the maximum frequency on this line is 1.5MHz.
Due to the minimum transfer delay allowed for NDS applications, the CLK minimum fre-
quency is 18MHz.
The clock controller generates two clocks (as shown in Figure 6 and Figure 7):
1. a clock for the CCLK: Four different sources can be used: CLK pin, DCCLK sig-
nal, CARDCK bit or A2/CK pin (in transparent mode).
2. a clock for DC/DC converter.
4234E–SCR–09/04
11
11 Page | ||
| Páginas | Total 42 Páginas | |
| PDF Descargar | [ Datasheet AT83C24-TISUM.PDF ] | |
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