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AT89LS51-16PC 데이터시트 PDF




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부품번호 AT89LS51-16PC 기능
기능 8-bit Low-Voltage Microcontroller with 4K Bytes In-System Programmable Flash
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AT89LS51-16PC 데이터시트, 핀배열, 회로
Features
Compatible with MCS-51® Products
4K Bytes of In-System Programmable (ISP) Flash Memory
– Endurance: 1000 Write/Erase Cycles
2.7V to 4.0V Operating Range
Fully Static Operation: 0 Hz to 16 MHz
Three-level Program Memory Lock
128 x 8-bit Internal RAM
32 Programmable I/O Lines
Two 16-bit Timer/Counters
Six Interrupt Sources
Full Duplex UART Serial Channel
Low-power Idle and Power-down Modes
Interrupt Recovery from Power-down Mode
Watchdog Timer
Dual Data Pointer
Power-off Flag
Flexible ISP Programming (Byte and Page Mode)
Description
The AT89LS51 is a low-voltage, high-performance CMOS 8-bit microcontroller with 4K
bytes of in-system programmable Flash memory. The device is manufactured using
Atmel’s high-density nonvolatile memory technology and is compatible with the indus-
try-standard 80C51 instruction set and pinout. The on-chip Flash allows the program
memory to be reprogrammed in-system or by a conventional nonvolatile memory pro-
grammer. By combining a versatile 8-bit CPU with in-system programmable Flash on a
monolithic chip, the Atmel AT89LS51 is a powerful microcontroller which provides a
highly-flexible and cost-effective solution to many embedded control applications.
The AT89LS51 provides the following standard features: 4K bytes of Flash, 128 bytes
of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a
five-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator,
and clock circuitry. In addition, the AT89LS51 is designed with static logic for operation
down to zero frequency and supports two software selectable power saving modes.
The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and
interrupt system to continue functioning. The Power-down mode saves the RAM con-
tents but freezes the oscillator, disabling all other chip functions until the next external
interrupt or hardware reset.
8-bit
Low-Voltage
Microcontroller
with 4K Bytes
In-System
Programmable
Flash
AT89LS51
Preliminary
Rev. 3053A–8051–05/02
1




AT89LS51-16PC pdf, 반도체, 판매, 대치품
Pin Description
VCC
GND
Port 0
Port 1
Port 2
Port 3
Supply voltage.
Ground.
Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight
TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance
inputs.
Port 0 can also be configured to be the multiplexed low-order address/data bus during
accesses to external program and data memory. In this mode, P0 has internal pull-ups.
Port 0 also receives the code bytes during Flash programming and outputs the code bytes
during program verification. External pull-ups are required during program verification.
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers can
sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the
internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being
pulled low will source current (IIL) because of the internal pull-ups.
Port 1 also receives the low-order address bytes during Flash programming and verification.
Port Pin
P1.5
P1.6
P1.7
Alternate Functions
MOSI (used for In-System Programming)
MISO (used for In-System Programming)
SCK (used for In-System Programming)
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers can
sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the
internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being
pulled low will source current (IIL) because of the internal pull-ups.
Port 2 emits the high-order address byte during fetches from external program memory and
during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this
application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external
data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Spe-
cial Function Register.
Port 2 also receives the high-order address bits and some control signals during Flash pro-
gramming and verification.
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can
sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the
internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being
pulled low will source current (IIL) because of the pull-ups.
Port 3 receives some control signals for Flash programming and verification.
Port 3 also serves the functions of various special features of the AT89LS51, as shown in the
following table.
4 AT89LS51
3053A–8051–05/02

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AT89LS51-16PC 전자부품, 판매, 대치품
AT89LS51
User software should not write 1s to these unlisted locations, since they may be used in future
products to invoke new features. In that case, the reset or inactive values of the new bits will
always be 0.
Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities
can be set for each of the five interrupt sources in the IP register.
Table 2. AUXR: Auxiliary Register
AUXR
Address = 8EH
Not Bit
Addressable
– – – WDIDLE
Bit 7 6 5 4
DISRTO
3
2
Reset Value = XXX00XX0B
– DISALE
10
DISALE
DISRTO
WDIDLE
WDIDLE
0
1
Reserved for future expansion
Disable/Enable ALE
DISALE
Operating Mode
0 ALE is emitted at a constant rate of 1/6 the oscillator frequency
1 ALE is active only during a MOVX or MOVC instruction
Disable/Enable Reset out
DISRTO
0 Reset pin is driven High after WDT times out
1 Reset pin is input only
Disable/Enable WDT in IDLE mode
WDT continues to count in IDLE mode
WDT halts counting in IDLE mode
Dual Data Pointer Registers: To facilitate accessing both internal and external data memory,
two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H-
83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1.
The user should always initialize the DPS bit to the appropriate value before accessing the
respective Data Pointer Register.
3053A–8051–05/02
7

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