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Número de pieza | AT89LV51-12AC | |
Descripción | 8-Bit Microcontroller with 4K Bytes Flash | |
Fabricantes | ATMEL Corporation | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de AT89LV51-12AC (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
No Preview Available ! Features
• Compatible with MCS-51™ Products
• 4K Bytes of Reprogrammable Flash Memory
– Endurance: 1,000 Write/Erase Cycles
• 2.7V to 6V Operating Range
• Fully Static Operation: 0 Hz to 12 MHz
• Three-Level Program Memory Lock
• 128 x 8-Bit Internal RAM
• 32 Programmable I/O Lines
• Two 16-Bit Timer/Counters
• Six Interrupt Sources
• Programmable Serial Channel
• Low Power Idle and Power Down Modes
Description
The AT89LV51 is a low-voltage, high-performance CMOS 8-bit microcomputer with
4K bytes of Flash Programmable and Erasable Read Only Memory. The device is
manufactured using Atmel’s high density nonvolatile memory technology and is com-
patible with the industry standard MCS-51™ instruction set and pinout. The on-chip
Flash allows the program memory to be reprogrammed in-system or by a conven-
tional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash
on a monolithic chip, the Atmel AT89LV51 is a powerful microcomputer which pro-
vides a highly flexible and cost effective solution to many embedded control applica-
tions. The AT89LV51 operates at 2.7 volts up to 6.0 volts.
Pin Configurations
(continued)
PDIP
TQFP
INDEX
CORNER
P1.5
P1.6
P1.7
RST
(RXD) P3.0
NC
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
4 44 34 24 14 03 93 83 73 63 53 4
1 33
2 32
3 31
4 30
5 29
6 28
7 27
8 26
9 25
10 24
11 23
1
21
31
1
4
51
61
71
1
8
9
2
0
2
12
2
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
NC
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
(RXD) P3.0
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
(WR) P3.6
(RD) P3.7
X TA L 2
X TA L 1
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VCC
39 P0.0 (AD0)
38 P0.1 (AD1)
37 P0.2 (AD2)
36 P0.3 (AD3)
35 P0.4 (AD4)
34 P0.5 (AD5)
33 P0.6 (AD6)
32 P0.7 (AD7)
31 EA/VPP
30 ALE/PROG
29 PSEN
28 P2.7 (A15)
27 P2.6 (A14)
26 P2.5 (A13)
25 P2.4 (A12)
24 P2.3 (A11)
23 P2.2 (A10)
22 P2.1 (A9)
21 P2.0 (A8)
PLCC
INDEX
CORNER
(RXD)
(TXD)
(INT0)
(INT1)
(T0)
(T1)
P1.5
P1.6
P1.7
RST
P3.0
NC
P3.1
P3.2
P3.3
P3.4
P3.5
6 4 2 44 42 40
7 5 3 1 43 4139
8 38
9 37
10 36
11 35
12 34
13 33
14 32
15 31
16 30
11781 92 02 12 22 32 42 52 62 72289
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
NC
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
8-Bit
Microcontroller
with 4K Bytes
Flash
AT89LV51
0303D-D–12/97
4-45
1 page AT89LV51
Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively,
of an inverting amplifier which can be configured for use as
an on-chip oscillator, as shown in Figure 1. Either a quartz
crystal or ceramic resonator may be used. To drive the
device from an external clock source, XTAL2 should be left
unconnected while XTAL1 is driven as shown in Figure 2.
There are no requirements on the duty cycle of the external
clock signal, since the input to the internal clocking circuitry
is through a divide-by-two flip-flop, but minimum and maxi-
mum voltage high and low time specifications must be
observed
Figure 1. Oscillator Connections
C2
C1
XTAL2
XTAL1
GND
Idle Mode
In idle mode, the CPU puts itself to sleep while all the on-
chip peripherals remain active. The mode is invoked by
software. The content of the on-chip RAM and all the spe-
cial functions registers remain unchanged during this
mode. The idle mode can be terminated by any enabled
interrupt or by a hardware reset.
It should be noted that when idle is terminated by a hard-
ware reset, the device normally resumes program execu-
tion, from where it left off, up to two machine cycles before
the internal reset algorithm takes control. On-chip hardware
inhibits access to internal RAM in this event, but access to
the port pins is not inhibited. To eliminate the possibility of
an unexpected write to a port pin when Idle is terminated by
reset, the instruction following the one that invokes Idle
should not be one that writes to a port pin or to external
memory.
Note: C1, C2 = 30 pF ± 10 pF for Crystals
= 40 pF ± 10 pF for Ceramic Resonators
Figure 2. External Clock Drive Configuration
NC XTAL2
EXTERNAL
OSCILLATOR
SIGNAL
XTAL1
GND
Power Down Mode
In the power down mode the oscillator is stopped, and the
instruction that invokes power down is the last instruction
executed. The on-chip RAM and Special Function Regis-
ters retain their values until the power down mode is termi-
nated. The only exit from power down is a hardware reset.
Reset redefines the SFRs but does not change the on-chip
RAM. The reset should not be activated before VCC is
restored to its normal operating level and must be held
active long enough to allow the oscillator to restart and sta-
bilize.
Status of External Pins During Idle and Power Down Modes
Mode
Idle
Idle
Power Down
Power Down
Program Memory
Internal
External
Internal
External
ALE
1
1
0
0
PSEN
1
1
0
0
PORT0
Data
Float
Data
Float
PORT1
Data
Data
Data
Data
PORT2
Data
Address
Data
Data
PORT3
Data
Data
Data
Data
4-49
5 Page AT89LV51
AC Characteristics
Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other
outputs = 80 pF.
External Program and Data Memory Characteristics
Symbol
Parameter
1/tCLCL
tLHLL
tAVLL
tLLAX
tLLIV
tLLPL
tPLPH
tPLIV
tPXIX
tPXIZ
tPXAV
tAVIV
tPLAZ
tRLRH
tWLWH
tRLDV
tRHDX
tRHDZ
tLLDV
tAVDV
tLLWL
tAVWL
tQVWX
tQVWH
tWHQX
tRLAZ
tWHLH
Oscillator Frequency
ALE Pulse Width
Address Valid to ALE Low
Address Hold After ALE Low
ALE Low to Valid Instruction In
ALE Low to PSEN Low
PSEN Pulse Width
PSEN Low to Valid Instruction In
Input Instruction Hold After PSEN
Input Instruction Float After PSEN
PSEN to Address Valid
Address to Valid Instruction In
PSEN Low to Address Float
RD Pulse Width
WR Pulse Width
RD Low to Valid Data In
Data Hold After RD
Data Float After RD
ALE Low to Valid Data In
Address to Valid Data In
ALE Low to RD or WR Low
Address to RD or WR Low
Data Valid to WR Transition
Data Valid to WR High
Data Hold After WR
RD Low to Address Float
RD or WR High to ALE High
12 MHz Oscillator
Min Max
127
43
48
233
43
205
145
0
59
75
312
10
400
400
252
0
97
517
585
200 300
203
23
433
33
0
43 123
Variable Oscillator
Min Max
0 12
2tCLCL-40
tCLCL-40
tCLCL-35
tCLCL-40
3tCLCL-45
0
4tCLCL-100
3tCLCL-105
tCLCL-8
tCLCL-25
5tCLCL-105
10
6tCLCL-100
6tCLCL-100
0
5tCLCL-165
3tCLCL-50
4tCLCL-130
tCLCL-60
7tCLCL-150
tCLCL-50
2tCLCL-70
8tCLCL-150
9tCLCL-165
3tCLCL+50
0
tCLCL-40
tCLCL+40
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4-55
11 Page |
Páginas | Total 16 Páginas | |
PDF Descargar | [ Datasheet AT89LV51-12AC.PDF ] |
Número de pieza | Descripción | Fabricantes |
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