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AT89S8252-16PA 데이터시트 PDF




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기능 8-Bit Microcontroller with 8K Bytes Flash
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AT89S8252-16PA 데이터시트, 핀배열, 회로
Features
Compatible with MCS-51™ Products
8K Bytes of In-System Reprogrammable Downloadable Flash Memory
– SPI Serial Interface for Program Downloading
– Endurance: 1,000 Write/Erase Cycles
2K Bytes EEPROM
– Endurance: 100,000 Write/Erase Cycles
4.0V to 6V Operating Range
Fully Static Operation: 0 Hz to 24 MHz
Three-Level Program Memory Lock
256 x 8-bit Internal RAM
32 Programmable I/O Lines
Three 16-bit Timer/Counters
Nine Interrupt Sources
Programmable UART Serial Channel
SPI Serial Interface
Low Power Idle and Power Down Modes
Interrupt Recovery From Power Down
Programmable Watchdog Timer
Dual Data Pointer
Power Off Flag
Description
The AT89S8252 is a low-power, high-performance CMOS 8-bit microcomputer with
8K bytes of Downloadable Flash programmable and erasable read only memory and
2K bytes of EEPROM. The device is manufactured using Atmel’s high density nonvol-
atile memory technology and is compatible with the industry standard 80C51 instruc-
tion set and pinout. The on-chip Downloadable Flash allows the program memory to
be reprogrammed in-system through an SPI serial interface or by a conventional non-
volatile memory programmer. By combining a versatile 8-bit CPU with Downloadable
Flash on a monolithic chip, the Atmel AT89S8252 is a powerful microcomputer which
provides a highly flexible and cost effective solution to many embedded control appli-
cations.
The AT89S8252 provides the following standard features: 8K bytes of Downloadable
Flash, 2K bytes of EEPROM, 256 bytes of RAM, 32 I/O lines, programmable watch-
dog timer, two Data Pointers, three 16-bit timer/counters, a six-vector two-level inter-
rupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In
addition, the AT89S8252 is designed with static logic for operation down to zero fre-
quency and supports two software selectable power saving modes. The Idle Mode
stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt sys-
tem to continue functioning. The Power Down Mode saves the RAM contents but
freezes the oscillator, disabling all other chip functions until the next interrupt or hard-
ware reset.
The Downloadable Flash can be changed a single byte at a time and is accessible
through the SPI serial interface. Holding RESET active forces the SPI bus into a serial
programming interface and allows the program memory to be written to or read from
unless Lock Bit 2 has been activated.
8-Bit
Microcontroller
with 8K Bytes
Flash
AT89S8252
0401D-A–12/97
4-105




AT89S8252-16PA pdf, 반도체, 판매, 대치품
Furthermore, P1.4, P1.5, P1.6, and P1.7 can be configured
as the SPI slave port select, data input/output and shift
clock input/output pins as shown in the following table.
Port Pin Alternate Functions
P1.0
T2 (external count input to Timer/Counter 2),
clock-out
P1.1
T2EX (Timer/Counter 2 capture/reload trigger
and direction control)
P1.4
SS (Slave port select input)
P1.5
MOSI (Master data output, slave data input pin
for SPI channel)
P1.6
MISO (Master data input, slave data output pin
for SPI channel)
P1.7
SCK (Master clock output, slave clock input pin
for SPI channel)
Port 1 also receives the low-order address bytes during
Flash programming and verification.
Port 2
Port 2 is an 8-bit bidirectional I/O port with internal pullups.
The Port 2 output buffers can sink/source four TTL inputs.
When 1s are written to Port 2 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 2 pins that are externally being pulled low will source
current (IIL) because of the internal pullups.
Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to
external data memory that use 16-bit addresses (MOVX @
DPTR). In this application, Port 2 uses strong internal pul-
lups when emitting 1s. During accesses to external data
memory that use 8-bit addresses (MOVX @ RI), Port 2
emits the contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits and some
control signals during Flash programming and verification.
Port 3
Port 3 is an 8 bit bidirectional I/O port with internal pullups.
The Port 3 output buffers can sink/source four TTL inputs.
When 1s are written to Port 3 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 3 pins that are externally being pulled low will source
current (IIL) because of the pullups.
Port 3 also serves the functions of various special features
of the AT89S8252, as shown in the following table.
Port 3 also receives some control signals for Flash pro-
gramming and verification.
Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Alternate Functions
RXD (serial input port)
TXD (serial output port)
INT0 (external interrupt 0)
INT1 (external interrupt 1)
T0 (timer 0 external input)
T1 (timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)
RST
Reset input. A high on this pin for two machine cycles while
the oscillator is running resets the device.
ALE/PROG
Address Latch Enable is an output pulse for latching the
low byte of the address during accesses to external mem-
ory. This pin is also the program pulse input (PROG) during
Flash programming.
In normal operation, ALE is emitted at a constant rate of 1/6
the oscillator frequency and may be used for external tim-
ing or clocking purposes. Note, however, that one ALE
pulse is skipped during each access to external data mem-
ory.
If desired, ALE operation can be disabled by setting bit 0 of
SFR location 8EH. With the bit set, ALE is active only dur-
ing a MOVX or MOVC instruction. Otherwise, the pin is
weakly pulled high. Setting the ALE-disable bit has no
effect if the microcontroller is in external execution mode.
PSEN
Program Store Enable is the read strobe to external pro-
gram memory.
When the AT89S8252 is executing code from external pro-
gram memory, PSEN is activated twice each machine
cycle, except that two PSEN activations are skipped during
each access to external data memory.
EA/VPP
External Access Enable. EA must be strapped to GND in
order to enable the device to fetch code from external pro-
gram memory locations starting at 0000H up to FFFFH.
Note, however, that if lock bit 1 is programmed, EA will be
internally latched on reset.
EA should be strapped to VCC for internal program execu-
tions. This pin also receives the 12-volt programming
enable voltage (VPP) during Flash programming when 12-
volt programming is selected.
4-108 AT89S8252

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AT89S8252-16PA 전자부품, 판매, 대치품
AT89S8252
Dual Data Pointer Registers To facilitate accessing both
internal EEPROM and external data memory, two banks of
16 bit Data Pointer Registers are provided: DP0 at SFR
address locations 82H-83H and DP1 at 84H-85H. Bit DPS
= 0 in SFR WMCON selects DP0 and DPS = 1 selects
DP1. The user should always initialize the DPS bit to the
appropriate value before accessing the respective Data
Pointer Register.
Power Off Flag The Power Off Flag (POF) is located at
bit_4 (PCON.4) in the PCON SFR. POF is set to “1” during
power up. It can be set and reset under software control
and is not affected by RESET.
Table 3. WMCON—Watchdog and Memory Control Register
WMCON Address = 96H
Reset Value = 0000 0010B
PS2
PS1
PS0
EEMWE
EEMEN
DPS
WDTRST
WDTEN
Bit 7 6 5 4 3 2 1 0
Symbol
PS2
PS1
PS0
EEMWE
EEMEN
DPS
WDTRST
RDY/BSY
WDTEN
Function
Prescaler Bits for the Watchdog Timer. When all three bits are set to “0”, the watchdog timer has a nominal period of 16
ms. When all three bits are set to “1”, the nominal period is 2048 ms.
EEPROM Data Memory Write Enable Bit. Set this bit to “1” before initiating byte write to on-chip EEPROM with the
MOVX instruction. User software should set this bit to “0” after EEPROM write is completed.
Internal EEPROM Access Enable. When EEMEN = 1, the MOVX instruction with DPTR will access on-chip EEPROM
instead of external data memory. When EEMEN = 0, MOVX with DPTR accesses external data memory.
Data Pointer Register Select. DPS = 0 selects the first bank of Data Pointer Register, DP0, and DPS = 1 selects the
second bank, DP1
Watchdog Timer Reset and EEPROM Ready/Busy Flag. Each time this bit is set to “1” by user software, a pulse is
generated to reset the watchdog timer. The WDTRST bit is then automatically reset to “0” in the next instruction cycle.
The WDTRST bit is Write-Only. This bit also serves as the RDY/BSY flag in a Read-Only mode during EEPROM write.
RDY/BSY = 1 means that the EEPROM is ready to be programmed. While programming operations are being executed,
the RDY/BSY bit equals “0” and is automatically reset to “1” when programming is completed.
Watchdog Timer Enable Bit. WDTEN = 1 enables the watchdog timer and WDTEN = 0 disables the watchdog timer.
4-111

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부품번호상세설명 및 기능제조사
AT89S8252-16PA

8-Bit Microcontroller with 8K Bytes Flash

ATMEL Corporation
ATMEL Corporation

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