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PDF AT90S1200-4YI Data sheet ( Hoja de datos )
| Número de pieza | AT90S1200-4YI | |
| Descripción | 8-Bit Microcontroller with 1K bytes In-System Programmable Flash | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Utilizes the AVR® RISC Architecture
• AVR – High-performance and Low-power RISC Architecture
– 89 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Up to 12 MIPS Throughput at 12 MHz
• Data and Non-volatile Program Memory
– 1K Byte of In-System Programmable Flash
Endurance: 1,000 Write/Erase Cycles
– 64 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program and EEPROM Data Security
• Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler
– On-chip Analog Comparator
– Programmable Watchdog Timer with On-chip Oscillator
– SPI Serial Interface for In-System Programming
• Special Microcontroller Features
– Low-power Idle and Power-down Modes
– External and Internal Interrupt Sources
– Selectable On-chip RC Oscillator for Zero External Components
• Specifications
– Low-power, High-speed CMOS Process Technology
– Fully Static Operation
• Power Consumption at 4 MHz, 3V, 25°C
– Active: 2.0 mA
– Idle Mode: 0.4 mA
– Power-down Mode: <1 µA
• I/O and Packages
– 15 Programmable I/O Lines
– 20-pin PDIP, SOIC and SSOP
• Operating Voltages
– 2.7 - 6.0V (AT90S1200-4)
– 4.0 - 6.0V (AT90S1200-12)
• Speed Grades
– 0 - 4 MHz, (AT90S1200-4)
– 0 - 12 MHz, (AT90S1200-12)
Pin Configuration
8-bit
Microcontroller
with 1K Byte
of In-System
Programmable
Flash
AT90S1200
Rev. 0838H–AVR–03/02
1
1 page  
Architectural
Overview
AT90S1200
The fast-access register file concept contains 32 x 8-bit general purpose working regis-
ters with a single clock cycle access time. This means that during one single clock cycle,
one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output from
the register file, the operation is executed, and the result is stored back in the register
file – in one clock cycle.
Figure 4. The AT90S1200 AVR RISC Architecture
0838H–AVR–03/02
The ALU supports arithmetic and logic functions between registers or between a con-
stant and a register. Single register operations are also executed in the ALU. Figure 4
shows the AT90S1200 AVR RISC microcontroller architecture. The AVR uses a Har-
vard architecture concept – with separate memories and buses for program and data
memories. The program memory is accessed with a 2-stage pipeline. While one instruc-
tion is being executed, the next instruction is pre-fetched from the program memory.
This concept enables instructions to be executed in every clock cycle. The program
memory is In-System Programmable Flash memory.
With the relative jump and relative call instructions, the whole 512 address space is
directly accessed. All AVR instructions have a single 16-bit word format, meaning that
every program memory address contains a single 16-bit instruction.
5
5 Page 
Status Register – SREG
AT90S1200
The AVR status register (SREG) at I/O space location $3F is defined as:
Bit
$3F
Read/Write
Initial Value
7
I
R/W
0
6
T
R/W
0
5
H
R/W
0
4
S
R/W
0
3
V
R/W
0
2
N
R/W
0
1
Z
R/W
0
0
C
R/W
0
SREG
• Bit 7 – I: Global Interrupt Enable
The global interrupt enable bit must be set (one) for the interrupts to be enabled. The
individual interrupt enable control is then performed in separate control registers. If the
global interrupt enable bit is cleared (zero), none of the interrupts are enabled indepen-
dent of the individual interrupt enable settings. The I-bit is cleared by hardware after an
interrupt has occurred, and is set by the RETI instruction to enable subsequent
interrupts.
• Bit 6 – T: Bit Copy Storage
The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source
and destination for the operated bit. A bit from a register in the register file can be copied
into T by the BST instruction, and a bit in T can be copied into a bit in a register in the
register file by the BLD instruction.
• Bit 5 – H: Half-carry Flag
The half-carry flag H indicates a half carry in some arithmetic operations. See the
Instruction Set description for detailed information.
• Bit 4 – S: Sign Bit, S = N⊕V
The S-bit is always an exclusive or between the negative flag N and the two’s comple-
ment overflow flag V. See the Instruction Set description for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The two’s complement overflow flag V supports two’s complement arithmetics. See the
Instruction Set description for detailed information.
• Bit 2 – N: Negative Flag
The negative flag N indicates a negative result after the different arithmetic and logic
operations. See the Instruction Set description for detailed information.
• Bit 1 – Z: Zero Flag
The zero flag Z indicates a zero result after the different arithmetic and logic operations.
See the Instruction Set description for detailed information.
• Bit 0 – C: Carry Flag
The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction
Set description for detailed information.
Note that the status register is not automatically stored when entering an interrupt rou-
tine and restored when returning from an interrupt routine. This must be handled by
software.
0838H–AVR–03/02
11
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| PDF Descargar | [ Datasheet AT90S1200-4YI.PDF ] | |
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