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PDF AT90S4414-8JI Data sheet ( Hoja de datos )
| Número de pieza | AT90S4414-8JI | |
| Descripción | 8-Bit Microcontroller with 4K bytes In-System Programmable Flash | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• AVR® - High Performance and Low Power RISC Architecture
• 118 Powerful Instructions - Most Single Clock Cycle Execution
• 4K bytes of In-System Reprogrammable Flash
– SPI Serial Interface for Program Downloading
– Endurance: 1,000 Write/Erase Cycles
• 256 bytes EEPROM
– Endurance: 100,000 Write/Erase Cycles
• 256 bytes Internal SRAM
• 32 x 8 General Purpose Working Registers
• 32 Programmable I/O Lines
• Programmable Serial UART
• SPI Serial Interface
• VCC: 2.7 - 6.0V
• Fully Static Operation
– 0 - 8 MHz, 4.0 - 6.0V
– 0 - 4 MHz, 2.7 - 4.0V
• Up to 8 MIPS Throughput at 8 MHz
• One 8-Bit Timer/Counter with Separate Prescaler
• One 16-Bit Timer/Counter with Separate Prescaler
and Compare and Capture Modes
• Dual PWM
• External and Internal Interrupt Sources
• Programmable Watchdog Timer with On-Chip Oscillator
• On-Chip Analog Comparator
• Low Power Idle and Power Down Modes
• Programming Lock for Software Security
Description
The AT90S4414 is a low-power CMOS 8-bit microcontroller based on the AVR
enhanced RISC architecture. By executing powerful instructions in a single clock
cycle, the AT90S4414 achieves throughputs approaching 1 MIPS per MHz allowing
the system designer to optimize power consumption versus processing speed.
The AVR core is based on an enhanced RISC architecture that combines a rich
instruction set with 32 general purpose working registers. All the 32 registers are
directly connected to the Arithmetic Logic Unit (ALU), allowing two independent regis-
ters to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster
than conventional CISC microcontrollers.
(continued)
8-Bit
Microcontroller
with 4K bytes
In-System
Programmable
Flash
AT90S4414
Preliminary
Pin Configurations
Rev. 0840DS–07/98
Note: This is a summary document. For the complete 76 page
datasheet, please visit
mail at literature@atme
our
l.co
web s
m and
ite at w
request
ww.atmel.com or e1-
literature #0840D.
1 page  
AT90S4414
have a single 16-bit word format. Every program memory
address contains a 16- or 32-bit instruction.
During interrupts and subroutine calls, the return address
program counter (PC) is stored on the stack. The stack is
effectively allocated in the general data SRAM, and conse-
quently the stack size is only limited by the total SRAM size
and the usage of the SRAM. All user programs must initial-
ize the SP in the reset routine (before subroutines or inter-
Figure 5. Memory Maps
rupts are executed). The 16-bit stack pointer SP is
read/write accessible in the I/O space.
The 256 bytes data SRAM can be easily accessed through
the five different addressing modes supported in the AVR
architecture.
The memory spaces in the AVR architecture are all linear
and regular memory maps.
A flexible interrupt module has its control registers in the
I/O space with an additional global interrupt enable bit in
the status register. All the different interrupts have a sepa-
rate interrupt vector in the interrupt vector table at the
beginning of the program memory. The different interrupts
have priority in accordance with their interrupt vector posi-
tion. The lower the interrupt vector address the higher prior-
ity.
5
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