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PDF AT91M40800 Data sheet ( Hoja de datos )
| Número de pieza | AT91M40800 | |
| Descripción | AT91 ARM Thumb Microcontrollers | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Incorporates the ARM7TDMI™ ARM® Thumb® Processor Core
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– Embedded ICE (In-Circuit Emulation)
• On-chip SRAM and/or ROM
– 32-bit Data Bus
– Single-clock Cycle Access
• Fully Programmable External Bus Interface (EBI)
– Maximum External Address Space of 64M Bytes
– Up to 8 Chip Selects
– Software Programmable 8/16-bit External Databus
• 8-level Priority, Individually Maskable, Vectored Interrupt Controller
– 4 External Interrupts, Including a High-priority Low-latency Interrupt Request
• 32 Programmable I/O Lines
• 3-channel 16-bit Timer/Counter
– 3 External Clock Inputs
– 2 Multi-purpose I/O Pins per Channel
• 2 USARTs
– 2 Dedicated Peripheral Data Controller (PDC) Channels per USART
• Programmable Watchdog Timer
• Advanced Power-saving Features
– CPU and Peripheral Can be Deactivated Individually
• Available in a 100-lead TQFP Package
Microcontroller
AT91M40800
AT91R40807
AT91M40807
AT91R40008
Primary SRAM Bank
8K Bytes
8K Bytes
8K Bytes
256K Bytes
Secondary SRAM Bank
–
128K Bytes
–
–
ROM
–
–
128K Bytes
–
AT91
ARM® Thumb®
Microcontrollers
AT91M40800
AT91R40807
AT91M40807
AT91R40008
Description
The AT91X40 Series is a subset of the Atmel AT91 16/32-bit microcontroller family,
which is based on the ARM7TDMI processor core. This processor has a high-perfor-
mance 32-bit RISC architecture with a high-density 16-bit instruction set and very low
power consumption. In addition, a large number of internally banked registers result in
very fast exception handling, making the device ideal for real-time control applications.
The AT91X40 Series features a direct connection to off-chip memory, including Flash,
through the fully programmable External Bus Interface (EBI). An eight-level priority
vectored interrupt controller, in conjunction with the Peripheral Data Controller signifi-
cantly improve the real-time performance of the device.
The devices are manufactured using Atmel’s high-density CMOS technology. By com-
bining the ARM7TDMI processor core with on-chip high-speed memory and a wide
range of peripheral functions on a monolithic chip, the Atmel AT91X40 Series is a fam-
ily of powerful microcontrollers that offer a flexible, cost-effective solution to many
compute-intensive embedded control applications.
Rev. 1354D–ATARM–08/02
1
1 page  
Architectural
Overview
Memories
Peripherals
System Peripherals
1354D–ATARM–08/02
AT91X40 Series
The AT91X40 Series Microcontrollers integrate an ARM7TDMI with its embedded ICE
interface, memories and peripherals. The series’ architecture consists of two main
buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB).
Designed for maximum performance and controlled by the memory controller, the ASB
interfaces the ARM7TDMI processor with the on-chip 32-bit memories, the External Bus
Interface (EBI) and the AMBA™ Bridge. The AMBA Bridge drives the APB, which is
designed for accesses to on-chip peripherals and optimized for low-power consumption.
The AT91X40 Series Microcontrollers implement the ICE port of the ARM7TDMI proces-
sor on dedicated pins, offering a complete, low-cost and easy-to-use debug solution for
target debugging.
The AT91X40 Series Microcontrollers embed up to 256K bytes of internal SRAM, and
up to 128K bytes of ROM. The internal memories are directly connected to the 32-bit
data bus and are single-cycle accessible. This provides maximum performance of 0.9
MIPS/MHz by using the ARM instruction set of the processor, minimizing system power
consumption and improving the performance of separate memory solutions.
The AT91X40 Series Microcontrollers feature an External Bus Interface (EBI), which
enables connection of external memories and application-specific peripherals. The EBI
supports 8- or 16-bit devices and can use two 8-bit devices to emulate a single 16-bit
device. The EBI implements the early read protocol, enabling faster memory accesses
than standard memory interfaces.
The AT91X40 Series Microcontrollers integrate several peripherals, which are classified
as system or user peripherals. All on-chip peripherals are 32-bit accessible by the
AMBA Bridge, and can be programmed with a minimum number of instructions. The
peripheral register set is composed of control, mode, data, status and enable/dis-
able/status registers.
An on-chip Peripheral Data Controller (PDC) transfers data between the on-chip
USARTs and on- and off-chip memories address space without processor intervention.
Most importantly, the PDC removes the processor interrupt handling overhead, making
it possible to transfer up to 64K continuous bytes without reprogramming the start
address, thus increasing the performance of the microcontroller, and reducing the power
consumption.
The External Bus Interface (EBI) controls the external memory or devices via an 8-bit or
16-bit data bus, and is programmed through the Advanced Peripheral Bus (APB). Each
chip select line has its own programming register.
The Power Saving (PS) module implements the Idle Mode (ARM7TDMI core clock
stopped until the next interrupt) and enables the user to adapt the power consumption of
the microcontroller to application requirements (independent peripheral clock control).
The Advanced Interrupt Controller (AIC) controls the internal sources from the internal
peripherals and the four external interrupt lines (including the FIQ) to provide an inter-
rupt and/or fast interrupt request to the ARM7TDMI. It integrates an 8-level priority
controller, and, using the Auto-vectoring feature, reduces the interrupt latency time.
The Parallel Input/Output Controller (PIO) controls up to 32 I/O lines. It enables the user
to select specific pins for on-chip peripheral input/output functions, and general-purpose
input/output signal pins. The PIO controller can be programmed to detect an interrupt on
a signal change from each line.
5
5 Page 
AT91X40 Series
External Bus Interface
Peripherals
Peripheral Registers
No abort is generated when reading the internal memory or by accessing the internal
peripheral, whether the address is defined or not.
When a write-protected area is accessed, the memory controller detects it and gener-
ates an abort but does not cancel the access.
The External Bus Interface handles the accesses between addresses 0x0040 0000 and
0xFFC0 0000. It generates the signals that control access to the external devices, and
can be configured from eight 1M byte banks up to four 16M bytes banks. It supports
byte, half-word and word aligned accesses.
For each of these banks, the user can program:
• Number of wait states
• Number of data float times (wait time after the access is finished to prevent any bus
contention in case the device is too long in releasing the bus)
• Data bus width (8-bit or 16-bit)
• With a 16-bit wide data bus, the user can program the EBI to control one 16-bit
device (Byte Access Select Mode) or two 8-bit devices in parallel that emulate a 16-
bit memory (Byte Write Access Mode).
The External Bus Interface features also the Early Read Protocol, configurable for all the
devices, that significantly reduces access time requirements on an external device in
the case of single clock cycle access.
The AT91X40 Series’ peripherals are connected to the 32-bit wide Advanced Peripheral
Bus. Peripheral registers are only word accessible – byte and half-word accesses are
not supported. If a byte or a half-word access is attempted, the memory controller auto-
matically masks the lowest address bits and generates a word access.
Each peripheral has a 16-Kbyte address space allocated (the AIC only has a 4-Kbyte
address space).
The following registers are common to all peripherals:
• Control Register – write only register that triggers a command when a one is written
to the corresponding position at the appropriate address. Writing a zero has no
effect.
• Mode Register – read/write register that defines the configuration of the peripheral.
Usually has a value of 0x0 after a reset.
• Data Registers – read and/or write register that enables the exchange of data
between the processor and the peripheral.
• Status Register – read only register that returns the status of the peripheral.
• Enable/Disable/Status Registers are shadow command registers. Writing a one in
the Enable Register sets the corresponding bit in the Status Register. Writing a one
in the Disable Register resets the corresponding bit and the result can be read in the
Status Register. Writing a bit to zero has no effect. This register access method
maximizes the efficiency of bit manipulation, and enables modification of a register
with a single non-interruptible instruction, replacing the costly read-modify-write
operation.
Unused bits in the peripheral registers are shown as “–“ and must be written at 0 for
upward compatibility. These bits read 0.
1354D–ATARM–08/02
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AT91M40800.PDF ] | |
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