PDF AT91RM9200 Data sheet ( Hoja de datos )

Número de pieza	AT91RM9200
Descripción	ARM920T- based Microcontroller
Fabricantes	ATMEL Corporation
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Features • Incorporates the ARM920T™ ARM® Thumb® Processor – 200 MIPS at 180 MHz, Memory Management Unit – 16-KByte Data Cache, 16-KByte Instruction Cache, Write Buffer – In-circuit Emulator including Debug Communication Channel – Mid-level Implementation Embedded Trace Macrocell™ (256-ball BGA Package only) • Low Power: On VDDCORE 24.4 mA in Normal Mode, 520 µA in Standby Mode • Additional Embedded Memories – 16K Bytes of SRAM and 128K Bytes of ROM • External Bus Interface (EBI) – Supports SDRAM, Static Memory, Burst Flash, Glueless Connection to CompactFlash® and NAND Flash/SmartMedia® • System Peripherals for Enhanced Performance: – Enhanced Clock Generator and Power Management Controller – Two On-chip Oscillators with Two PLLs – Very Slow Clock Operating Mode and Software Power Optimization Capabilities – Four Programmable External Clock Signals – System Timer Including Periodic Interrupt, Watchdog and Second Counter – Real-time Clock with Alarm Interrupt – Debug Unit, Two-wire UART and Support for Debug Communication Channel – Advanced Interrupt Controller with 8-level Priority, Individually Maskable Vectored Interrupt Sources, Spurious Interrupt Protected – Seven External Interrupt Sources and One Fast Interrupt Source – Four 32-bit PIO Controllers with Up to 122 Programmable I/O Lines, Input Change Interrupt and Open-drain Capability on Each Line – 20-channel Peripheral DMA Controller (PDC) • Ethernet MAC 10/100 Base-T – Media Independent Interface (MII) or Reduced Media Independent Interface (RMII) – Integrated 28-byte FIFOs and Dedicated DMA Channels for Receive and Transmit • USB 2.0 Full Speed (12 Mbits per second) Host Double Port – Dual On-chip Transceivers (Single Port Only on 208-lead PQFP Package) – Integrated FIFOs and Dedicated DMA Channels • USB 2.0 Full Speed (12 Mbits per second) Device Port – On-chip Transceiver, 2-Kbyte Configurable Integrated FIFOs • Multimedia Card Interface (MCI) – Automatic Protocol Control and Fast Automatic Data Transfers – MMC and SD Memory Card-compliant, Supports Up to Two SD Memory Cards • Three Synchronous Serial Controllers (SSC) – Independent Clock and Frame Sync Signals for Each Receiver and Transmitter – I2S Analog Interface Support, Time Division Multiplex Support – High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer • Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART) – Support for ISO7816 T0/T1 Smart Card – Hardware Handshaking – RS485 Support, IrDA® Up To 115 Kbps – Full Modem Control Lines on USART1 • Master/Slave Serial Peripheral Interface (SPI) – 8- to 16-bit Programmable Data Length, 4 External Peripheral Chip Selects ARM920T-based Microcontroller AT91RM9200 NOTE: This is a summary document. The complete document is available on the Atmel website at www.atmel.com. 1768MS–ATARM–09-Jul-09 1 page AT91RM9200 Table 3-1. Signal Description by Peripheral Pin Name BMS DRXD DTXD IRQ0 - IRQ6 FIQ PA0 - PA31 PB0 - PB29 PC0 - PC31 PD0 - PD27 D0 - D31 A0 - A25 NCS0 - NCS7 NWR0 - NWR3 NOE NRD NUB NLB NWE NWAIT NBS0 - NBS3 CFCE1 - CFCE2 CFOE CFWE CFIOR CFIOW CFRNW CFCS Function Type Memory Controller Boot Mode Select Input Debug Unit Debug Receive Data Input Debug Transmit Data Output AIC External Interrupt Inputs Input Fast Interrupt Input Input PIO Parallel IO Controller A I/O Parallel IO Controller B I/O Parallel IO Controller C I/O Parallel IO Controller D I/O EBI Data Bus I/O Address Bus Output SMC Chip Select Lines Output Write Signal Output Output Enable Output Read Signal Output Upper Byte Select Output Lower Byte Select Output Write Enable Output Wait Signal Input Byte Mask Signal Output EBI for CompactFlash Support CompactFlash Chip Enable Output CompactFlash Output Enable Output CompactFlash Write Enable Output CompactFlash IO Read Output CompactFlash IO Write Output CompactFlash Read Not Write Output CompactFlash Chip Select Output Active Level Comments Debug Receive Data Debug Transmit Data Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset 0 at reset Low 1 at reset Low 1 at reset Low 1 at reset Low 1 at reset Low 1 at reset Low 1 at reset Low 1 at reset Low Low 1 at reset Low Low Low Low Low Low 1768MS–ATARM–09-Jul-09 5 5 Page AT91RM9200 4.4 256-ball BGA Package Pinout Table 4-2. AT91RM9200 Pinout for 256-ball BGA Package Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name A1 TDI C3 PD14 E5 TCK G14 PA1 A2 JTAGSEL C4 PB22 E6 GND G15 PA2 A3 PB20 C5 PB19 E7 PB15 G16 PA3 A4 PB17 C6 PD10 E8 GND G17 XIN32 A5 PD11 C7 PB13 E9 PB7 H1 PD23 A6 PD8 C8 PB12 E10 PB3 H2 PD20 A7 VDDIOP C9 PB6 E11 PA29 H3 PD22 A8 PB9 C10 PB1 E12 PA26 H4 PD21 A9 PB4 C11 GND E13 PA25 H5 VDDIOP A10 PA31/BMS C12 PA20 E14 PA9 H13 VDDPLL A11 VDDIOP C13 PA18 E15 PA6 H14 VDDIOP A12 PA23 C14 VDDCORE E16 PD3 H15 GNDPLL A13 PA19 C15 GND E17 PD0 H16 GND A14 GND C16 PA8 F1 PD16 H17 XOUT32 A15 PA14 C17 PD5 F2 GND J1 PD25 A16 VDDIOP D1 TST1 F3 PB23 J2 PD27 A17 PA13 D2 VDDIOP F4 PB25 J3 PD24 B1 TDO D3 VDDIOP F5 PB24 J4 PD26 B2 PD13 D4 GND F6 VDDCORE J5 PB28 B3 PB18 D5 VDDIOP F7 PB16 J6 PB29 B4 PB21 D6 PD7 F9 PB11 J12 GND B5 PD12 D7 PB14 F11 PA30 J13 GNDOSC B6 PD9 D8 VDDIOP F12 PA28 J14 VDDOSC B7 GND D9 PB8 F13 PA4 J15 VDDPLL B8 PB10 D10 PB2 F14 PD2 J16 GNDPLL B9 PB5 D11 GND F15 PD1 J17 XIN B10 PB0 D12 PA22 F16 PA5 K1 HDPA B11 VDDIOP D13 PA21 F17 PLLRCB K2 DDM B12 PA24 D14 PA16 G1 PD19 K3 HDMA B13 PA17 D15 PA10 G2 PD17 K4 VDDIOP B14 PA15 D16 PD6 G3 GND K5 DDP B15 PA11 D17 PD4 G4 PB26 K13 PC5 B16 PA12 E1 NRST G5 PD18 K14 PC4 B17 PA7 E2 NTRST G6 PB27 K15 PC6 C1 TMS E3 GND G12 PA27 K16 VDDIOM C2 PD15 E4 TST0 G13 PA0 K17 XOUT 1768MS–ATARM–09-Jul-09 11 11 Page

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