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PDF AT91SAM7A2 Data sheet ( Hoja de datos )
| Número de pieza | AT91SAM7A2 | |
| Descripción | ARM Thumb - based Microcontrollers | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• ARM7TDMI® ARM® Thumb® Processor Core
– High Performance 32-bit RISC
– High-density 16-bit Instruction set (Thumb)
– Leader in MIPS/Watt
– Embedded ICE (In Circuit Emulation)
• 16 Kbytes Internal SRAM
• Fully Programmable External Bus Interface (EBI)
– Maximum External Address Space of 6 Mbytes, Up to Four Chip Select Lines
• 8-level Priority, Vectored Interrupt Controller
– Three External Interrupts Including One Fast Interrupt Line
• Ten Channel Peripheral Data Controller (PDC)
• 57 Programmable I/O Lines
• Four 16-bit General Purpose Timers (GPT)
– Three Configurable Modes: Counter, PWM, Capture
– Four External Clock Inputs, Three Multi-purpose I/O Pins per Timer
• Four 16-bit Simple Timers (ST)
• Four Channel 16-bit Pulse Width Modulation (PWM)
• Four CAN Controllers 2.0A and 2.0B Full CAN
– One with 32 Buffers, Three with 16 Buffers
• Two USARTs
– Support for J1587 and LIN Protocols
• One Master/Slave SPI Interface
– 8 to 16-bit Programmable Data Length
– Four External Serial Peripheral Chip Selects
• Two 8-channel 10-bit Analog to Digital Converters (ADC)
• Two 16-bit Capture Modules (CAPT)
• Programmable Watch Timer (WT)
• Programmable Watchdog (WD)
• Power Management Controller (PMC)
– 32 kHz Oscillator, Main Oscillator and PLL
• IEEE 1149.1 JTAG Boundary-scan on all Digital Pins
• Fully Static Operation: 0 Hz to 30 MHz at VDDCORE=3.3V, 85°C
• 3.0V to 5.5V Operating Voltage Range
• 3.0V to 3.6V Core, Memory and Analog Voltage Range
• -40° to +85°C Operating Temperature Range
• Available in a 176-lead LQFP Package
AT91 ARM®
Thumb®- based
Microcontrollers
AT91SAM7A2
Summary
Description
The AT91SAM7A2 is based on the ARM7TDMI embedded processor. This processor
has a high-performance 32-bit RISC architecture with a high-density 16-bit instruction
set and very low power consumption.
In addition, a large number of internally banked registers result in very fast exception
handling, making the device ideal for real-time control applications.
The AT91SAM7A2 has a direct connection to off-chip memory, including Flash,
through the fully programmable External Bus Interface.
An 8-level priority vectored Interrupt Controller in conjunction with the Peripheral Data
Controller significantly improves the real time performance of the device. The device
is manufactured using high-density CMOS technology.
By combining the ARM7TDMI processor with an on-chip SRAM, and a wide range of
peripheral functions, including USART, SPI, CAN Controllers, Timer Counter and Ana-
log-to-Digital Converters, on a monolithic chip, the AT91SAM7A2 is a powerful device
that provides a flexible, cost-effective solution to many compute-intensive embedded
control applications in the automotive and industrial world.
6021AS–ATARM–03/04
Note: This is a summary document. A complete document
is in preparation.
1 page  
AT91SAM7A2 - Summary
Signal Description
Table 2. Signal Description
Module
Name
Function
ADD[19:1]
External address bus
ADD0/NLB
External address line line/
Lower byte enable
ADD20/CS3
External address line/ Chip select
D[15:0]
External data bus
EBI NOE
Output enable
NWR0/NWE
Write enable
NCS[2:0]
Chip select lines
NWR1/NUB
Upper byte enable
NWAIT
External Wait
CORECLK
Core CLock
IRQ[1:0]
GIC
FIQ
External interrupt lines
Fast interrupt line
Power-on
Reset
NRESET
Hardware reset input
MCKI
Master clock input
Master Clock MCKO
Master clock output
PLLRC
PLL RC network input
32.768 kHz RTCKI
clock
RTCKO
32.768 KHz clock input
32.768 KHz clock output
PIO
UPIO[31:0]
General purpose I/O
SCK0/MPIO
USART0 clock line
USART0
RXD0/MPIO
USART0 receive line
TXD0/MPIO
USART0 transmit line
SCK1/MPIO
USART1 clock line
USART1
RXD1/MPIO
USART1 receive line
TXD1/MPIO
USART1 transmit line
Capture0 CAPT0
Capture input
Capture1 CAPT1
Capture input
PWM
PWM[3:0]
Pulse Width Modulation output
T0TIOA[2:0]/MPIO Capture/waveform I/O
Timer T0
T0TIOB[2:0]/MPIO Trigger/waveform I/O
T0TIOCLK[2:0]/MP External clock/trigger/input
IO
Active
Type Level Comments
O (Z)(1)
O L (Z)
O H (Z)
The EBI is tri-stated when NRESET is at a
I/O (Z) logical low level.
O L (Z) Internal pull-downs on data bus bits
O L (Z)
O L (Z)
O L (Z)
I L Disable at reset, multiplexed with UPIO30
O Disable at reset, multiplexed with UPIO31
I
I
I L Schmitt input with internal filter
I
Connected to external crystal (4 to 6 Mhz)
O
I
I Connected to external 32.768 Khz crystal
O
I/O (Z)
I/O (Z) Multiplexed with general purpose I/O
I/O (Z) Multiplexed with general purpose I/O
I/O (Z) Multiplexed with general purpose I/O
I/O (Z) Multiplexed with general purpose I/O
I/O (Z) Multiplexed with general purpose I/O
I/O (Z) Multiplexed with general purpose I/O
I
I
O (L)
I/O (Z) Multiplexed with a general purpose I/O
I/O (Z) Multiplexed with a general purpose I/O
I/O (Z) Multiplexed with a general purpose I/O
6021AS–ATARM–03/04
5
5 Page 
Ordering
Information
Table 3. Ordering Information
Ordering Code
AT91SAM7A2-AI
AT91SAM7A2 - Summary
Package
TQFP 176
Temperature Operating Range
Industrial
(-40°C to +85°C)
6021AS–ATARM–03/04
11
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| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet AT91SAM7A2.PDF ] | |
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