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AT34C02N-10SC-1.8 데이터시트 PDF




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기능 2-Wire Serial EEPROM with Permanent Software Write Protect
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AT34C02N-10SC-1.8 데이터시트, 핀배열, 회로
Features
Permanent Software Write Protection for the First-Half of the Array
– Software Procedure to Verify Write Protect Status
Hardware Write Protection for the Entire Array
Low Voltage and Standard Voltage Operation
– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
Internally Organized 256 x 8
2-Wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
100 KHz (1.8V and 2.7V) and 400 KHz (5.0V) Compatibility
16-Byte Page Write Modes
Partial Page Writes Are Allowed
Self-Timed Write Cycle (10 ms max)
High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
– ESD Protection: >3,000V
Automotive Grade and Extended Temperature Devices Available
8-Pin PDIP, 8-Pin JEDEC SOIC and 8-Pin TSSOP Packages
Description
The AT34C02 provides 2048 bits of serial electrically erasable and programmable
read only memory (EEPROM) organized as 256 words of 8 bits each. The first-half of
the device incorporates a software write protection feature while hardware write pro-
tection for the entire array is available via an external pin as well. Once the software
write protection is enabled, by sending a special command to the device, it cannot be
reversed. The hardware write protection is controlled with the WP pin and can be used
to protect the entire array, whether or not the software write protection has been
enabled. This allows the user to protect none, first-half, or all of the array depending
on the application. The device is optimized for use in many industrial and commercial
applications where low power and low voltage operations are essential. The AT34C02
is available in space saving 8-pin PDIP, 8-pin JEDEC SOIC, and 8-pin TSSOP pack-
ages and is accessed via a 2-wire serial interface. In addition, it is available in 5.0V
(4.5V to 5.5V), 2.7V (2.7V to 5.5V), and 1.8V (1.8V to 5.5V) versions.
Pin Configurations
Pin Name
A0 to A2
SDA
SCL
WP
Function
Address Inputs
Serial Data
Serial Clock Input
Write Protect
8-Pin SOIC
A0
A1
A2
GND
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
8-Pin TSSOP
8-Pin PDIP
A0
A1
A2
GND
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
A0
A1
A2
GND
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
2-Wire Serial
EEPROM
with Permanent
Software Write
Protect
2K (256 x 8)
AT34C02
2-Wire Serial
EEPROM with
Permanent
Software Write
Protec
Rev. 0958D–07/98
1




AT34C02N-10SC-1.8 pdf, 반도체, 판매, 대치품
AC Characteristics
Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +1.8V to +5.5V,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
1.8V, 2.7V
Symbol
Parameter
Min Max
fSCL
tLOW
tHIGH
tI
tAA
tBUF
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
tF
tSU.STO
tDH
tWR
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time(1)
Clock Low to Data Out Valid
Time the bus must be free before a new transmission can start(1)
Start Hold Time
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time(1)
Inputs Fall Time(1)
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
100
4.7
4.0
100
0.1 4.5
4.7
4.0
4.7
0
200
1.0
300
4.7
100
10
Endurance(1)
5.0V, 25°C, Page Mode
1M
Note: 1. This parameter is characterized and is not 100% tested.
5.0V
Min Max
400
1.2
0.6
50
0.1 0.9
1.2
0.6
0.6
0
100
0.3
300
0.6
50
10
1M
Units
kHz
µs
µs
ns
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
ms
Write
Cycles
Memory Organization
AT34C02, 2K Serial EEPROM: The 2K is internally orga-
nized with 256 pages of 1 byte each. Random word
addressing requires a 8-bit data word address.
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is nor-
mally pulled high with an external device. Data on the SDA
pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL
high periods will indicate a start or stop condition as defined
below.
START CONDITION: A high-to-low transition of SDA with
SCL high is a start condition which must precede any other
command (refer to Start and Stop Definition timing dia-
gram).
STOP CONDITION: A low-to-high transition of SDA with
SCL high is a stop condition. After a read sequence, the
stop command will place the EEPROM in a standby power
mode (refer to Start and Stop Definition timing diagram).
ACKNOWLEDGE: All addresses and data words are seri-
ally transmitted to and from the EEPROM in 8-bit words.
The EEPROM sends a zero to acknowledge that it has
received each word. This happens during the ninth clock
cycle.
STANDBY MODE: The AT34C02 features a low power
standby mode which is enabled: (a) upon power-up or (b)
after the receipt of the STOP bit and the completion of any
internal operations.
MEMORY RESET: After an interruption in protocol, power
loss or system reset, any 2-wire part can be reset by follow-
ing these steps:
(a) Clock up to 9 cycles, (b) look for SDA high in each cycle
while SCL is high and then (c) create a start condition as
SDA is high.
4 AT34C02

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AT34C02N-10SC-1.8 전자부품, 판매, 대치품
AT34C02
Device Addressing
The 2K EEPROM device requires an 8-bit device address
word following a start condition to enable the chip for a read
or write operation (refer to Figure 2).
The device address word consists of a mandatory one-zero
sequence for the first four most-significant bits (1010) for
normal read and write operations and 0110 for writing to
the write protect register.
The next 3 bits are the A2, A1 and A0 device address bits
for the AT34C02 EEPROM. These 3 bits must compare to
their corresponding hard-wired input pins.
The eighth bit of the device address is the read/write opera-
tion select bit. A read operation is initiated if this bit is high
and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will
output a zero. If a compare is not made, the chip will return
to a standby state. The device will not acknowledge if the
write protect register has been programmed and the control
code is 0110.
Write Operations
BYTE WRITE: A write operation requires an 8-bit data
word address following the device address word and
acknowledgment. Upon receipt of this address, the
EEPROM will again respond with a zero and then clock in
the first 8-bit data word. Following receipt of the 8-bit data
word, the EEPROM will output a zero and the addressing
device, such as a microcontroller, must terminate the write
sequence with a stop condition. At this time the EEPROM
enters an internally-timed write cycle, tWR, to the nonvolatile
memory. All inputs are disabled during this write cycle and
the EEPROM will not respond until the write is complete
(refer to Figure 3).
The device will acknowledge a write command, but not
write the data, if the software or hardware write protection
has been enabled. The write cycle time must be observed
even when the write protection is enabled.
PAGE WRITE: The 2K device is capable of 16-byte page
write.
A page write is initiated the same as a byte write, but the
microcontroller does not send a stop condition after the first
data word is clocked in. Instead, after the EEPROM
acknowledges receipt of the first data word, the microcon-
troller can transmit up to fifteen more data words. The
EEPROM will respond with a zero after each data word
received. The microcontroller must terminate the page
write sequence with a stop condition (refer to Figure 4).
The data word address lower four bits are internally incre-
mented following the receipt of each data word. The higher
data word address bits are not incremented, retaining the
memory page row location. When the word address, inter-
nally generated, reaches the page boundary, the following
byte is placed at the beginning of the same page. If more
than sixteen data words are transmitted to the EEPROM,
the data word address will “roll over” and previous data will
be overwritten. The address “roll over” during write is from
the last byte of the current page to the first byte of the same
page.
The device will acknowledge a write command, but not
write the data, if the software or hardware write protection
has been enabled. The write cycle time must be observed
even when the write protection is enabled.
ACKNOWLEDGE POLLING: Once the internally-timed
write cycle has started and the EEPROM inputs are dis-
abled, acknowledge polling can be initiated. This involves
sending a start condition followed by the device address
word. The read/write bit is representative of the operation
desired. Only if the internal write cycle has completed will
the EEPROM respond with a zero allowing the read or write
sequence to continue.
Write Protection
The software write protection, once enabled, permanently
write protects only the first-half of the array (00H - 7FH)
while the hardware write protection, via the WP pin, is used
to protect the entire array.
SOFTWARE WRITE PROTECTION: The software write
protection is enabled by sending a command, similar to a
normal write command, to the device which programs the
write protect register. This must be done with the WP pin
low. The write protect register is programmed by sending a
write command with the device address of 0110 instead of
1010 with the address and data bit being don’t cares (refer
to Figure 1). Once the software write protection has been
enabled, the device will no longer acknowledge the 0110
control byte. The software write protection cannot be
reversed even if the device is powered down. The write
cycle time must be observed.
HARDWARE WRITE PROTECTION: The WP pin can be
connected to VCC, GND, or left floating. Connecting the WP
pin to VCC will write protect the entire array, regardless of
whether or not the software write protection has been
enabled. The software write protection register cannot be
programmed when the WP pin is connected to VCC. If the
WP pin is connected to GND or left floating, the write pro-
tection mode is determined by the status of the software
write protect register.
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부품번호상세설명 및 기능제조사
AT34C02N-10SC-1.8

2-Wire Serial EEPROM with Permanent Software Write Protect

ATMEL Corporation
ATMEL Corporation

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