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AT43USB351M 데이터시트 PDF




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AT43USB351M 데이터시트, 핀배열, 회로
Features
AVR® Microcontroller-based Function Controller
Fully Programmable USB Low/Full-speed Function with Five Endpoints
High Performance and Low Power 1.5/12/24 MIPs AVR RISC Microcontroller
120 Powerful Instructions – Most with 83 ns Execution Cycle Times
24 KB Masked ROM Program Memory
1 KB Internal SRAM
32 x 8 General-purpose Working Registers
19 Programmable I/O Port Pins
12 Channels 10-bit A-to-D Converter
Programmable SPI Serial Interface
One 8-bit Timer Counter with Separate Pre-scaler
One 16-bit Timer Counter with Separate Pre-scaler and Two PWMs
External and Internal Interrupt Sources
Programmable Watchdog Timer
Low Power Idle and Power-down Modes
6 MHz Crystal Oscillator with PLL
5V Operation with On-chip 3.3V Regulators
48-lead LQFP Package
Binary-compatible with the AT43USB355
Description
The Atmel AT43USB351M is a USB AVR-based microcontroller that is configurable as
a low-speed or full-speed USB device. Its program memory is a 24-Kbyte mask pro-
grammable ROM and its data memory is 1-Kbyte SRAM. The on-chip peripherals
consists of 19 general-purpose I/O ports, two timer-counters, SPI serial interface, a
PWM and a 10-bit AD converter with 12 input channels.www.DataSheet4U.com
The MCU of the AT43USB351M is a high performance 8-bit AVR RISC that operates
at a clock frequency of 1.5 MHz, 12 MHz or 24 MHz. The A-to-D converter has a min-
imum conversion time of 12 µs that together with the 12 input channel should cover
even the most demanding game controllers such as gamepads, joysticks and racing
wheels. The two PWM outputs can be programmed for 8-, 9- or 10-bit resolution for
applications requiring force feedback. The 19 general-purpose programmable I/O pins
provide generous inputs for the various buttons and switches and LED indicators that
are being used in increasing numbers in today's game controllers.
The USB function has one control endpoint and four additional programmable end-
points, each with their own FIFOs. Two of the endpoints have a 64-byte FIFO each,
while the other two have 8-byte FIFOs. The USB hardware supports the physical and
link layers of the USB protocol while the transaction layer function must be imple-
mented in the MCU's fir mware. The AVR architecture was developed to be
programmed in C efficiently and without loss in performance.
The AT43USB351M is binary-compatible with the AT43USB355. Program develop-
ment and debugging for the AT43USB351M uses the AT43DK355 and all its tools and
libraries.
Full-speed/
Low-speed
USB
Microcontroller
with ADC and
PWM
AT43USB351M
Summary
Rev. 3302CS–USB–2/04
1




AT43USB351M pdf, 반도체, 판매, 대치품
Signal Description
Name
Type
VCC1, 2
VCCA
VSS1, 2
VSSA
CEXT1,2
Power Supply/Ground
Power Supply/Ground
Power Supply/Ground
Power Supply/Ground
Power Supply/Ground
CEXT
Power Supply/Ground
XTAL1
XTAL2
LFT
Input
Output
Input
DPO
DMO
PA[0:7]
PB[4:7]
Bi-directional
Bi-directional
Bi-directional
Bi-directional
PD[0:6]
Bi-directional
ADC[0:11]
TEST
RESETN
2XN
Input
Input
Input
Input
Function
5V Digital Power Supply
5V Power Supply for the ADC
Digital Ground
Ground for the ADC
External Capacitors for Power Supplies – High quality 2.2 µF capacitors must be
connected to V331 and V332 for proper operation of the chip.
External Capacitor for Analog Power Supply – A high quality 0.33 µF capacitor
must be connected to V33A for proper operation of the chip.
Oscillator Input – Input to the inverting oscillator amplifier.
Oscillator Output – Output of the inverting oscillator amplifier.
PLL Filter – For proper operation of the PLL, this pin should be connected through
a 0.01 µF capacitor in parallel with a 100resistor in series with a 0.1 µF capacitor
to ground (VSS). Both capacitors must be high quality ceramic.
Upstream Plus USB I/O – This pin should be connected to CEXT1 through an
external 1.5 k.
Upstream Minus USB I/O
Port A[0:7] – Bi-directional 8-bit I/O port with 2 mA drive strength and a
programmable pull-up resistor.
Port B[4:7] – Bi-directional 8-bit I/O port with 2 mA drive strength and a
programmable pull-up resistor. PB[4:7] have dual functions as shown below:
Port Pin
Alternate Function
PB4 SSN, SPI Slave Port Select or SCL, I2C Serial Bus Clock
PB5 MOSI, SPI Slave Port Select Input
PB6 MISO, SPI Master Data In, Slave Data Out
PB7 SCK, SPI Master Clock Out, Slave Clock In
Port D[0:6] – Bi-directional I/O ports with 2 mA drive strength and a programmable
pull-up resistor. PortD[2:6] have dual functions as shown below:
Port Pin
Alternate Function
PD2
INT0, External Interrupt 0
PD4
ICP, Timer/Counter, Input Capture
PD3
INT1, External Interrupt 1
PD5
OC1A Timer/Counter1 Output Compare A
PD6
OC1B Timer/Counter1 Output Compare B
ADC Input[0:11] – 12-bit input pins for the ADC.
Test Pin – This pin should be tied to ground.
Reset – Active Low.
Clock Frequency Selector (see Table 1 on page 6)
4 AT43USB351M
3302CS–USB–2/04

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AT43USB351M 전자부품, 판매, 대치품
Development
Support
AT43USB351M
lowest Data Space addresses ($00 - $1 F), allowing them to be accessed as though they were
ordinary memory locations.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis-
ters, Timer/Counters, and other I/O functions. The I/O Memory can be accessed directly, or as
the Data Space locations following those of the register file, $20 - $5F.
The AVR uses a Harvard architecture concept – with separate memories and buses for pro-
gram and data. The program memory is executed with a single-level pipelining. While one
instruction is being executed, the next instruction is pre-fetched from the program memory.
This concept enables instructions to be executed in every clock cycle. The program memory is
a downloadable SRAM or a mask programmed ROM.
With the relative jump and call instructions, the whole 24K address space is directly accessed.
Most AVR instructions have a single 16-bit word format. Every program memory address con-
tains a 16- or 32-bit instruction.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on
the stack. The stack is effectively allocated in the general data SRAM, and consequently, the
stack size is only limited by the total SRAM size and the usage of the SRAM. All user pro-
grams must initialize the Stack Pointer (SP) in the reset routine (before subroutines or
interrupts are executed). The 10-bit SP is read/write accessible in the I/O space.
The 1-Kbyte data SRAM can be easily accessed through the five different addressing modes
supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps. A flexi-
ble interrupt module has its control registers in the I/O space with an additional global interrupt
enable bit in the status register. All interrupts have a separate interrupt vector in the interrupt
vector table at the beginning of the program memory. The interrupts have priority in accor-
dance with their interrupt vector position. The lower the interrupt vector address, the higher the
priority.
The AT43USB351M uses the same program and development tools as the AT43USB355 and
other Atmel AVR microcontrollers, including: C compilers, macro assemblers, program debug-
gers/simulators and in-circuit emulators. The AT43DK355 development kit is also available,
including firmware source code for the most common USB applications.
3302CS–USB–2/04
7

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Missed Watchdog Timer Reset

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