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AT45DB041B-RI 데이터시트 PDF




ATMEL Corporation에서 제조한 전자 부품 AT45DB041B-RI은 전자 산업 및 응용 분야에서
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부품번호 AT45DB041B-RI 기능
기능 4-megabit 2.5-volt Only or 2.7-volt Only DataFlash
제조업체 ATMEL Corporation
로고 ATMEL Corporation 로고


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AT45DB041B-RI 데이터시트, 핀배열, 회로
Features
Single 2.5V - 3.6V or 2.7V - 3.6V Supply
Serial Peripheral Interface (SPI) Compatible
20 MHz Max Clock Frequency
Page Program Operation
– Single Cycle Reprogram (Erase and Program)
– 2048 Pages (264 Bytes/Page) Main Memory
Supports Page and Block Erase Operations
Two 264-byte SRAM Data Buffers – Allows Receiving of Data
while Reprogramming of Nonvolatile Memory
Continuous Read Capability through Entire Array
Low Power Dissipation
– 4 mA Active Read Current Typical
– 2 µA CMOS Standby Current Typical
Hardware Data Protection Feature
100% Compatible to AT45DB041 and AT45DB041A
5.0V-tolerant Inputs: SI, SCK, CS, RESET, and WP Pins
Commercial and Industrial Temperature Ranges
4-megabit
2.5-volt Only or
2.7-volt Only
DataFlash®
Description
The AT45DB041B is a 2.5-volt or 2.7-volt only, serial interface Flash memory ideally
suited for a wide variety of digital voice-, image-, program code- and data-storage
applications. Its 4,325,376 bits of memory are organized as 2048 pages of 264 bytes
each. In addition to the main memory, the AT45DB041B also contains two SRAM data
buffers of 264 bytes each. The buffers allow receiving of data while a page in the main
memory is being reprogrammed, as well as reading or writing a continuous
data stream. EEPROM emulation (bit or byte alterability) is easily handled with a self-
AT45DB041B
Pin Configurations
Pin Name Function
CS Chip Select
SCK
Serial Clock
SI Serial Input
SO Serial Output
WP
RESET
Hardware Page Write
Protect Pin
Chip Reset
RDY/BUSY Ready/Busy
8-SOIC
SI
SCK
RESET
CS
1
2
3
4
8 SO
7 GND
6 VCC
5 WP
RDY/BUSY
RESET
WP
NC
NC
VCC
GND
NC
NC
NC
CS
SCK
SI
SO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TSOP Top View
Type 1
28 NC
27 NC
26 NC
25 NC
24 NC
23 NC
22 NC
21 NC
20 NC
19 NC
18 NC
17 NC
16 NC
15 NC
28-SOIC
GND
NC
NC
CS
SCK
SI
SO
NC
NC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VCC
27 NC
26 NC
25 WP
24 RESET
23 RDY/BUSY
22 NC
21 NC
20 NC
19 NC
18 NC
17 NC
16 NC
15 NC
CBGA Top View
through Package
12 3
A
NC NC
B
SCK GND VCC
C
CS RDY/BSY WP
D
SO SI RESET
E
NC NC NC
Rev. 1938F–DFLSH–10/02
1




AT45DB041B-RI pdf, 반도체, 판매, 대치품
cycle, allowing one continuous read operation without the need of additional address
sequences. To perform a continuous read, an opcode of 68H or E8H must be clocked
into the device followed by 24 address bits and 32 don’t care bits. The first four bits of
the 24-bit address sequence are reserved for upward and downward compatibility to
larger and smaller density devices (see Notes under “Command Sequence for
Read/Write Operations” diagram). The next 11 address bits (PA10 - PA0) specify which
page of the main memory array to read, and the last nine bits (BA8 - BA0) of the 24-bit
address sequence specify the starting byte address within the page. The 32 don’t care
bits that follow the 24 address bits are needed to initialize the read operation. Following
the 32 don’t care bits, additional clock pulses on the SCK pin will result in serial data
being output on the SO (serial output) pin.
The CS pin must remain low during the loading of the opcode, the address bits, the don’t
care bits, and the reading of data. When the end of a page in main memory is reached
during a Continuous Array Read, the device will continue reading at the beginning of the
next page with no delays incurred during the page boundary crossover (the crossover
from the end of one page to the beginning of the next page). When the last bit in the
main memory array has been read, the device will continue reading back at the begin-
ning of the first page of memory. As with crossing over page boundaries, no delays will
be incurred when wrapping around from the end of the array to the beginning of the
array.
A low-to-high transition on the CS pin will terminate the read operation and tri-state the
SO pin. The maximum SCK frequency allowable for the Continuous Array Read is
defined by the fCAR specification. The Continuous Array Read bypasses both data buff-
ers and leaves the contents of the buffers unchanged.
MAIN MEMORY PAGE READ: A Main Memory Page Read allows the user to read data
directly from any one of the 2048 pages in the main memory, bypassing both of the data
buffers and leaving the contents of the buffers unchanged. To start a page read, an
opcode of 52H or D2H must be clocked into the device followed by 24 address bits and
32 don’t care bits. The first four bits of the 24-bit address sequence are reserved bits,
the next 11 address bits (PA10 - PA0) specify the page address, and the next nine
address bits (BA8 - BA0) specify the starting byte address within the page. The 32 don’t
care bits which follow the 24 address bits are sent to initialize the read operation. Fol-
lowing the 32 don’t care bits, additional pulses on SCK result in serial data being output
on the SO (serial output) pin. The CS pin must remain low during the loading of the
opcode, the address bits, the don’t care bits, and the reading of data. When the end of a
page in main memory is reached during a Main Memory Page Read, the device will con-
tinue reading at the beginning of the same page. A low-to-high transition on the CS pin
will terminate the read operation and tri-state the SO pin.
BUFFER READ: Data can be read from either one of the two buffers, using different
opcodes to specify which buffer to read from. An opcode of 54H or D4H is used to read
data from buffer 1, and an opcode of 56H or D6H is used to read data from buffer 2. To
perform a Buffer Read, the eight bits of the opcode must be followed by 15 don’t care
bits, nine address bits, and eight don’t care bits. Since the buffer size is 264 bytes, nine
address bits (BFA8 - BFA0) are required to specify the first byte of data to be read from
the buffer. The CS pin must remain low during the loading of the opcode, the address
bits, the don’t care bits, and the reading of data. When the end of a buffer is reached,
the device will continue reading back at the beginning of the buffer. A low-to-high transi-
tion on the CS pin will terminate the read operation and tri-state the SO pin.
STATUS REGISTER READ: The status register can be used to determine the device’s
Ready/Busy status, the result of a Main Memory Page to Buffer Compare operation, or
the device density. To read the status register, an opcode of 57H or D7H must be
4 AT45DB041B
1938F–DFLSH–10/02

4페이지










AT45DB041B-RI 전자부품, 판매, 대치품
AT45DB041B
Additional Commands
MAIN MEMORY PAGE PROGRAM THROUGH BUFFER: This operation is a combina-
tion of the Buffer Write and Buffer to Main Memory Page Program with Built-in Erase
operations. Data is first shifted into buffer 1 or buffer 2 from the SI pin and then pro-
grammed into a specified page in the main memory. To initiate the operation, an 8-bit
opcode, 82H for buffer 1 or 85H for buffer 2, must be followed by the four reserved bits
and 20 address bits. The 11 most significant address bits (PA10 - PA0) select the page
in the main memory where data is to be written, and the next nine address bits
(BFA8 - BFA0) select the first byte in the buffer to be written. After all address bits are
shifted in, the part will take data from the SI pin and store it in one of the data buffers. If
the end of the buffer is reached, the device will wrap around back to the beginning of the
buffer. When there is a low-to-high transition on the CS pin, the part will first erase the
selected page in main memory to all 1s and then program the data stored in the buffer
into the specified page in the main memory. Both the erase and the programming of the
page are internally self-timed and should take place in a maximum of time tEP. During
this time, the status register will indicate that the part is busy.
MAIN MEMORY PAGE TO BUFFER TRANSFER: A page of data can be transferred
from the main memory to either buffer 1 or buffer 2. To start the operation, an 8-bit
opcode, 53H for buffer 1 and 55H for buffer 2, must be followed by the four reserved
bits, 11 address bits (PA10 - PA0) which specify the page in main memory that is to be
transferred, and nine don’t care bits. The CS pin must be low while toggling the SCK pin
to load the opcode, the address bits, and the don’t care bits from the SI pin. The transfer
of the page of data from the main memory to the buffer will begin when the CS pin tran-
sitions from a low to a high state. During the transfer of a page of data (tXFR), the status
register can be read to determine whether the transfer has been completed or not.
MAIN MEMORY PAGE TO BUFFER COMPARE: A page of data in main memory can
be compared to the data in buffer 1 or buffer 2. To initiate the operation, an 8-bit opcode,
60H for buffer 1 and 61H for buffer 2, must be followed by 24 address bits consisting of
the four reserved bits, 11 address bits (PA10 - PA0) which specify the page in the main
memory that is to be compared to the buffer, and nine don’t care bits. The CS pin must
be low while toggling the SCK pin to load the opcode, the address bits, and the don’t
care bits from the SI pin. On the low-to-high transition of the CS pin, the 264 bytes in the
selected main memory page will be compared with the 264 bytes in buffer 1 or buffer 2.
During this time (tXFR), the status register will indicate that the part is busy. On comple-
tion of the compare operation, bit 6 of the status register is updated with the result of the
compare.
AUTO PAGE REWRITE: This mode is only needed if multiple bytes within a page or
multiple pages of data are modified in a random fashion. This mode is a combination of
two operations: Main Memory Page to Buffer Transfer and Buffer to Main Memory Page
Program with Built-in Erase. A page of data is first transferred from the main memory to
buffer 1 or buffer 2, and then the same data (from buffer 1 or buffer 2) is programmed
back into its original page of main memory. To start the rewrite operation, an 8-bit
opcode, 58H for buffer 1 or 59H for buffer 2, must be followed by the four reserved bits,
11 address bits (PA10 - PA0) that specify the page in main memory to be rewritten, and
nine additional don’t care bits. When a low-to-high transition occurs on the CS pin, the
part will first transfer data from the page in main memory to a buffer and then program
the data from the buffer back into same page of main memory. The operation is inter-
nally self-timed and should take place in a maximum time of tEP. During this time, the
status register will indicate that the part is busy.
1938F–DFLSH–10/02
7

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