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PDF AT45DB080-TI Data sheet ( Hoja de datos )
| Número de pieza | AT45DB080-TI | |
| Descripción | 8-Megabit 2.7-volt Only Sequential Access Parallel I/O DataFlash | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Single 2.7V - 3.6V Supply
• Sequential Access, Parallel I/O Architecture
• Page Program Operation
– Single Cycle Reprogram (Erase and Program)
– 4096 Pages (264 Bytes/Page) Main Memory
• Two 264-Byte Data Buffers – Allows Receiving of Data while
Reprogramming of Non-Volatile Memory
• Internal Program and Control Timer
• Fast Page Program Time – 7 ms Typical
• 120 µs Typical Page to Buffer Transfer Time
• Low Power Dissipation
– 4 mA Active Read Current Typical
– 2 µA CMOS Standby Current Typical
• 2 MHz Max Clock Frequency
• Hardware Data Protection Feature
• Synchronous Clocking (Two Modes)
• CMOS and TTL Compatible Inputs and Outputs
• Commercial and Industrial Temperature Ranges
Description
The AT45DB080 is a 2.7-volt only, sequential access, parallel interface Flash memory
suitable for in-system reprogramming. Its 8,650,752 bits of memory are organized as
4096 pages of 264-bytes each. In addition to the main memory, the AT45DB080 also
contains two data buffers of 264-bytes each. The buffers allow receiving of data while
a page in the main memory is being reprogrammed. Unlike conventional Flash memo-
ries that are accessed randomly with multiple address lines and a parallel interface,
Pin Configurations
(continued)
Pin Name
CS
CLK
I/O7-I/O0
WP
RESET
RDY/BUSY
Function
Chip Select
Clock
Input/Output
Hardware Page
Write Protect Pin
Chip Reset
Ready/Busy
SOIC
GND
NC
NC
CS
CLK
DC
DC
NC
NC
I/O0
I/O1
I/O2
I/O3
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VCC
27 NC
26 NC
25 WP
24 RESET
23 RDY/BUSY
22 NC
21 NC
20 NC
19 I/O7
18 I/O6
17 I/O5
16 I/O4
15 VCC
TSOP Top View
Type 1
RDY/BUSY
RESET
WP
NC
NC
NC
VCC
GND
NC
NC
NC
NC
CS
CLK
DC
DC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 NC
31 NC
30 NC
29 I/O7
28 I/O6
27 I/O5
26 I/O4
25 VCC
24 GND
23 I/O3
22 I/O2
21 I/O1
20 I/O0
19 NC
18 NC
17 NC
Note: SOIC pins 6 and 7 and TSOP pins 15 and 16 are DON’T CONNECT.
8-Megabit
2.7-volt Only
Sequential
Access
Parallel I/O
DataFlash®
AT45DB080
Preliminary
Rev. 1075B–06/98
1
1 page  
AT45DB080
can be loaded into buffer 2 (or vice versa). See application
note AN-4 (“Using Atmel’s Serial DataFlash”) for more
details.
HARDWARE PAGE WRITE PROTECT: If the WP pin is
held low, the first 256 pages of the main memory cannot be
reprogrammed. The only way to reprogram the first 256
pages is to first drive the protect pin high and then use the
program commands previously mentioned. The WP pin is
internally pulled high; therefore, in low pin count applica-
tions, connection of the WP pin is not necessary if this pin
and feature will not be utilized. However, it is recom-
mended that the WP pin be driven high externally when-
ever possible.
RESET: A low state on the reset pin (RESET) will terminate
the operation in progress and reset the internal state
machine to an idle state. The device will remain in the reset
condition as long as a low level is present on the RESET
pin. Normal operation can resume once the RESET pin is
brought back to a high level.
The device incorporates an internal power-on reset circuit,
so there are no restrictions on the RESET pin during
power-on sequences. The RESET pin is also internally
pulled high; therefore, in low pin count applications, con-
nection of the RESET pin is not necessary if this pin and
Absolute Maximum Ratings*
Temperature Under Bias.......................-55°C to +125°C
Storage Temperature............................-65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground......................... -0.6V to +6.25V
All Output Voltages
with Respect to Ground................... -0.6V to VCC + 0.6V
feature will not be utilized. However, it is recommended
that the RESET pin be driven high externally whenever
possible.
READY/BUSY: This open drain output pin will be driven
low when the device is busy in an internally self-timed oper-
ation. This pin, which is normally in a high state (through an
external pull-up resistor), will be pulled low during program-
ming operations, compare operations, and during page-to-
buffer transfers.
The busy status indicates that the Flash memory array and
one of the buffers cannot be accessed; read and write
operations to the other buffer can still be performed.
Power On/Reset State
When power is first applied to the device, or when recover-
ing from a reset condition, the device will default to the
“Inactive Clock Polarity High” mode. In addition, the output
pins (I/O7 - I/O0) will be in a high impedance state, and a
high to low transition on the CS pin will be required to start
a valid instruction. The Clock Polarity mode will be auto-
matically selected on every falling edge of CS by sampling
the inactive clock state.
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
DC and AC Operating Range
AT45DB081
Operating Temperature (Case)
Com.
Ind.
0°C to 70°C
-40°C to 85°C
VCC Power Supply(1)
2.7V to 3.6V
Note: 1. After power is applied and VCC is at the minimum specified data sheet value, the system should wait 20 ms before an oper-
ational mode is started.
5
5 Page 
AT45DB080
Detailed Read Timing – Inactive Clock Polarity Low
Main Memory Page Read
CS
CLK
I/O7-I/O0
(INPUT)
I/O7-I/O0
(OUTPUT)
1 2345
60 61 62 63 64 65 66 67
tSU
CMD ADDR ADDR ADDR X
XXXXX
HIGH-IMPEDANCE
tV
DATA OUT
DATA DATA DATA
Buffer Read
CS
CLK
I/O7-I/O0
(INPUT)
I/O7-I/O0
(OUTPUT)
1 2345678
tSU
CMD ADDR ADDR ADDR
HIGH-IMPEDANCE
X
tV
DATA OUT
DATA DATA DATA
Status Register Read
CS
CLK
1 234
tSU
I/O7-I/O0
(INPUT)
I/O7-I/O0
(OUTPUT)
CMD
tV
HIGH-IMPEDANCE
HIGH-IMPEDANCE
DATA DATA DATA
STATUS REGISTER
OUTPUT
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet AT45DB080-TI.PDF ] | |
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