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PDF AT45DB1282-CC Data sheet ( Hoja de datos )
| Número de pieza | AT45DB1282-CC | |
| Descripción | 128-megabit 2.7-volt Dual-interface DataFlash | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Single 2.7V - 3.6V Supply
• Dual-interface Architecture
– RapidS™ Serial Interface: 40 MHz Maximum Clock Frequency
(SPI Modes 0 and 3 Compatible for Frequencies up to 33 MHz)
– Rapid8™ 8-bit Interface: 20 MHz Maximum Clock Frequency
• Page Program Operation
– Dedicated Intelligent Programming Operation
– 16,384 Pages (1,056 Bytes/Page) Main Memory
• Automated Page and Block Erase Operations
• Two 1056-byte SRAM Data Buffers – Allows Receiving of Data
while Reprogramming the Flash Array
• Continuous Read Capability through Entire Array
– Ideal for Code Shadowing Applications
• Low-power Dissipation
– 10 mA Active Read Current Typical – Serial Interface
– 12 mA Active Read Current Typical – 8-bit Interface
– 5 µA CMOS Standby Current Typical
• Hardware Data Protection
• Security: 128-byte Security Register
– 64-byte User Programmable Space
– Unique 64-byte Device Identifier
• 100,000 Program/Erase Cycles Per Page Typical
• Data Retention – 10 Years
• Commercial and Industrial Temperature Ranges
Description
The AT45DB1282 is a 2.7-volt, dual-interface sequential access Flash memory ideally
suited for a wide variety of digital voice-, image-, program code- and data-storage
Pin Configurations
Pin Name
CS
SCK/CLK
SI
SO
I/O7 - I/O0
WP
RESET
RDY/BUSY
SER/BYTE
Function
Chip Select
Serial Clock/Clock
Serial Input
Serial Output
8-bit Input/Output
Hardware Page Write
Protect Pin
Chip Reset
Ready/Busy
Serial/8-bit Interface
Control
Note:
*Optional Use – See pin description text
for connection information.
TSOP Top View: Type 1
NC
NC
RDY/BUSY
RESET
WP
NC
NC
NC
VCC
GND
NC
NC
NC
NC
CS
SCK
SI*
SO*
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 NC
39 NC
38 NC
37 NC
36 NC
35 I/O7*
34 I/O6*
33 I/O5*
32 I/O4*
31 VCCP*
30 GNDP*
29 I/O3*
28 I/O2*
27 I/O1*
26 I/O0*
25 SER/BYTE*
24 CLK
23 NC
22 NC
21 NC
CBGA Top View
1 23 45
A
B
C
NC SER/BYTE NC I/O7 I/O6
D
I/O2 SCK/CLK GND VCC I/O5
E
I/O1 CS RDY/BUSY WP I/O4
F
I/O0 SO SI RESET I/O3
G
NC GNDP VCCP NC NC
H
J
128-megabit
2.7-volt
Dual-interface
DataFlash®
AT45DB1282
Preliminary
™
Rev. 2472C–DFLSH–11/03
1
1 page  
AT45DB1282
Program and Erase Commands
BUFFER WRITE: Data can be clocked in from the input pins (SI or I/O7 - I/O0) into
either buffer 1 or buffer 2. To load data into either buffer, a 1-byte opcode, 84H for buffer
1 or 87H for buffer 2, must be clocked into the device, followed by four address bytes
comprised of 21 don’t care bits and 11 buffer address bits (BFA10 - BFA0). The 11
buffer address bits specify the first byte in the buffer to be written. After the last address
byte has been clocked into the device, data can then be clocked in on subsequent clock
cycles. If the end of the data buffer is reached, the device will wrap around back to the
beginning of the buffer. Data will continue to be loaded into the buffer until a low-to-high
transition is detected on the CS pin.
BUFFER TO MAIN MEMORY PAGE PROGRAM: A previously-erased page within main
memory can be programmed with the contents of either buffer 1 or buffer 2. The pro-
gramming time is selectable by the system through the use of different opcodes
between a normal mode and a fast mode (the fast program option will consume more
current). A 1-byte opcode, 88H for buffer 1 or 89H for buffer 2 (98H for buffer 1 fast pro-
gram or 99H for buffer 2 fast program), must be clocked into the device followed by four
address bytes consisting of 7 don’t care bits, 14 page address bits (PA13 - PA0) that
specify the page in the main memory to be written and 11 don’t care bits. When a low-to-
high transition occurs on the CS pin, the part will program the data stored in the buffer
into the specified page in the main memory. It is necessary that the page in main mem-
ory that is being programmed has been previously erased using one of the erase
commands (Page Erase or Block Erase). The programming of the page is internally self-
timed and should take place in a maximum time of tP for normal programming or tFP for
fast programming. During this time, the status register and the RDY/BUSY pin will indi-
cate that the part is busy.
PAGE ERASE: The Page Erase command can be used to individually erase any page
in the main memory array allowing the Buffer to Main Memory Page Program to be uti-
lized at a later time. To perform a page erase, an opcode of 81H must be loaded into the
device, followed by four address bytes comprised of 7 don’t care bits, 14 page address
bits (PA13 - PA0) that specify the page in the main memory to be erased and 11 don’t
care bits. When a low-to-high transition occurs on the CS pin, the part will erase the
selected page (the erased state is a logical 1). The erase operation is internally self-
timed and should take place in a maximum time of tPE. During this time, the status regis-
ter and the RDY/BUSY pin will indicate that the part is busy.
BLOCK ERASE: A block of eight pages can be erased at one time. This command is
useful when large amounts of data has to be written into the device. This will avoid using
multiple Page Erase Commands. To perform a block erase, an opcode of 50H must be
loaded into the device, followed by four address bytes comprised of 7 don’t care bits, 11
page address bits (PA13 -PA3) and 14 don’t care bits. The 11 page address bits are
used to specify which block of eight pages is to be erased. When a low-to-high transition
occurs on the CS pin, the part will erase the selected block of eight pages. The erase
operation is internally self-timed and should take place in a maximum time of tBE. During
this time, the status register and the RDY/BUSY pin will indicate that the part is busy.
2472C–DFLSH–11/03
5
5 Page 
AT45DB1282
commands previously mentioned. If this pin and feature are not utilized it is recom-
mended that the WP pin be driven high externally.
RESET: A low state on the reset pin (RESET) will terminate the operation in progress
and reset the internal state machine to an idle state. The device will remain in the reset
condition as long as a low level is present on the RESET pin. Normal operation can
resume once the RESET pin is brought back to a high level.
The device incorporates an internal power-on reset circuit, so there are no restrictions
on the RESET pin during power-on sequences. If this pin and feature are not utilized it is
recommended that the RESET pin be driven high externally.
READY/BUSY: This open drain output pin will be driven low when the device is busy in
an internally self-timed operation. This pin, which is normally in a high state (through
an external pull-up resistor), will be pulled low during programming/erase operations,
compare operations, and page-to-buffer transfers.
The busy status indicates that the Flash memory array and one of the buffers cannot be
accessed; read and write operations to the other buffer can still be performed.
8-BIT PORT SUPPLY VOLTAGE (VCCP AND GNDP): The VCCP and GNDP pins are
used to supply power for the 8-bit input/output pins (I/O7-I/O0). The VCCP and GNDP
pins need to be used if the 8-bit port is to be utilized; however, these pins should be
treated as “don’t connects” if the SER/BYTE pin is not connected or if the SER/BYTE pin
is always driven high externally.
Power-on/Reset State
When power is first applied to the device, or when recovering from a reset condition, the
device will default to Mode 3. In addition, the output pins (SO or I/O7 - I/O0) will be in a
high impedance state, and a high-to-low transition on the CS pin will be required to start
a valid instruction. The mode (Mode 3 or Mode 0) will be automatically selected on every
falling edge of CS by sampling the inactive clock state. After power is applied and VCC is
at the minimum datasheet value, the system should wait 20 ms before an operational
mode is started.
System
Considerations
The RapidS serial interface is controlled by the serial clock SCK, serial input SI and chip
select CS pins. The sequential 8-bit Rapid8 is controlled by the clock CLK, 8 I/Os and
chip select CS pins. These signals must rise and fall monotonically and be free from
noise. Excessive noise or ringing on these pins can be misinterpreted as multiple edges
and cause improper operation of the device. The PC board traces must be kept to a
minimum distance or appropriately terminated to ensure proper operation. If necessary,
decoupling capacitors can be added on these pins to provide filtering against noise
glitches.
As system complexity continues to increase, voltage regulation is becoming more
important. A key element of any voltage regulation scheme is its current sourcing capa-
bility. Like all Flash memories, the peak current for DataFlash occur during the
programming and erase operation. The regulator needs to supply this peak current
requirement. An under specified regulator can cause current starvation. Besides
increasing system noise, current starvation during programming or erase can lead to
improper operation and possible data corruption.
2472C–DFLSH–11/03
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AT45DB1282-CC.PDF ] | |
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