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PDF AT48802-16QC Data sheet ( Hoja de datos )
| Número de pieza | AT48802-16QC | |
| Descripción | Spread- Spectrum Signal Processor Integrated Circuit | |
| Fabricantes | ATMEL Corporation | |
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AT48802
Features
Two Independent PN (Pseudo-Random Noise) Generators
• Programmable R7 (128) to R13 (8,192) PN Sequence Lengths
• Programmable Tau-Dither Amplitude
• Programmable PN Phase Adjustment to 1/16 Chip
• Correlation Acquisition Interface
• Programming Register Control
• Microcontroller Compatible Bus Interface
• Patent-Pending Frequency Diversity
•• Low Speed Link Data Path for Supervisory and Setup Functions
Description
The AT48802 Spread-Spectrum Signal Processor (SSSP) chip from Atmel handles
all PN code generation, synchronization, and handshaking required for either station
(handset or base station) of a time division duplex direct sequence spread-spectrum
cordless telephone. The AT48802 supports RF spreading and despreading for the
best rejection of interference. In conjunction with a single-chip microcontroller, the
circuit performs the following functions:
• Generates a pseudo-random sequence for spreading the transmitted signal.
• Generates a pseudo-random sequence for despreading in the receiver.
• Generates a sliding phase PN for acquiring synchronization with an incoming
signal.
• Controls receive signal strength measurement timing for correlation peak
detection.
• Operates a tau-dither tracking loop, with adaptive threshold, to maintain
synchronization with the incoming signal.
• Controls transmit keying antenna switching for time-division duplexing.
Pin Configuration
(continued)
64 Lead PQFP
Spread-
Spectrum
Signal
Processor
Integrated
Circuit
Preliminary
0624A
2-1
1 page  
AT48802
Time Division Duplex Architecture
The AT48802 processor supports a Time Division Duplex
(TDD) mode of operation where the transceiver transmits
information during one time period and receives during an
alternating time period. This architecture has the benefit of
optimizing the frequency channel utilization as the trans-
mit and receive frequencies can be equal to or close to
one another, without spreading at two frequencies that are
wide apart. The chip generates all TDD signals, (including
those signals that account for time delays through the RF
transceiver) that are necessary to implement a full-duplex
voice communication system. All internal timing is derived
from a master external clock. The chip is fully static and
can work at any clock frequency less than 20 MHz. In all
the following discussions the clock rate is assumed to be
15.360 MHz which is available from the companion RF
module.
The 15.360 MHz master clock is internally divided down to
a 7.5 kHz TDD rate, alternating between transmit cycle
and receive cycle. That is, the transmit and receive cycles
last for 66.67µs.
Sleep Mode and Battery Functionality
In most battery applications it is necessary to power down
one end of the communication link except when a call is to
be made. The sleep mode circuits of the AT48802 control
this function.
The sleep mode circuits consist of a timer which runs from
a low frequency (4 kHz) RC oscillator and a set of latches
to interact with the rest of the chip which runs from the high
frequency clock input. The sleep mode circuits also can
also disable and protect the I/O’s of the high frequency
circuits. The protected mode is such that the outputs are
three-stated and the input is floating. In addition, the sleep
control section has a DC power control output which can
be used to shutdown external circuits VCC.
The chip should always be connected to VCC in order for
the sleep mode to be usable; the sleep mode circuits are
alive and running as long as VCC is applied, however their
power drain is extremely small.
The sleep circuits will wake-up the chip, and other circuits
if desired, in any one of three ways.
1. Time-out from the 4 kHz Oscillator will happen about
2 seconds (one half cycle of divided by 214 ) after go-
ing to sleep. Then the remote set could, for example,
briefly listen for an incoming call using narrowband re-
ception (which has little or no acquisition time), and
listen for a predetermined tone with a very narrow-
band filter. For different wake-up periods the value of
the C can be changed.
2. If the INTERCOM input is activated. The edge sense
is programmable at R6 b7.
3. If the FLIPSW input is activated. The edge sense is
programmable at R11 b7.
When the chip wakes up it stores information about the
reason for wake-up in the I/O Registers at R14 b0-2 so the
microprocessor can respond in a suitable way. The edge
sense for FLIPSW and INTERCOM are programmed at
R14 b4-5. (Note: Throughout this document “Rx by”
means Register x bit y; x is hexadecimal.)
Once the chip is awake, only the microprocessor can put
it back into sleep mode. It does this through the bus port
at R0 b7. The OPERATE bit must be set before the com-
mand to STANDBY can be recognized. If the chip is
awake and the user activates the INTERCOM or FLIPSW
inputs, then the microprocessor can sense these actions
at R14 b4-5.
Figure 1. Sleep Mode Arrangement
VCC
High Speed I/Os
High Speed
Processing
Circuits
Sleep Mode Circuits
High Speed I/Os
(Operate/!Standby
and Wake 0, Wake 1)
2-5
5 Page 
AT48802
TDD Rate
R9 b7, when set low, causes the TDD rate to be normal
7500 Hz. When set high, the TDD rate is 1875 Hz. This
mode can cause the transmit signal to be 1875 Hz square
wave AM. This is useful when the handset must wake-up
and detect whether it is being signaled in a very short time.
If the PN is turned off then the receive microcontroller can
be setup as a very narrow 1875 Hz filter and detector to
decide very quickly if the base is signaling the handset. If
not, it may go back to sleep.
When in 1875 Hz TDD mode, delays and pulse widths of
RSSI, AUD T/H, AUX T/H and internal data path timing do
not change, and still work in normal specified manner, so
this mode is only for very specialized use.
Port 0
Port 0 is a general purpose register output port of the
AT48802. It is suitable for various housekeeping functions
of a telephone such as making LED indicators turn on,
driving a DTMF generator, keypad sensor, etc. This port is
accessed through R7 b0-7 and its outputs appear on pins
2 through 6 and 12 through 14 of the chip.
Test Aids
Sync Output
The SYNC pin 52 can be used to observe the timing of TX
PN epoch and/or RX PN epoch. The functionality is con-
trolled by R9 b0-1. The pulse indicates when the gener-
ators start their PN codes, which are called the epochs.
When a chip phase lock is achieved, the syncs are almost
coincident.
Alternate Port 0
General purpose output port 0 bits 0-3 can be pro-
grammed in normal operation by writing to register 7. Al-
ternate usage of these bits for engineering test purposes
is enabled and disabled by first writing the desired configu-
ration to register 13 (decimal 19). Note that in each case,
a zero bit in register 13 enables the standard configuration
for the ASIC port 0 outputs.
Table 1. Port bit 0.0 alternate usage:
P0.0
Reg 0x13 bits [3:2]
00
01
10
11
Test Selector P0.0 Function
Follows P0.0 (Reg 7 bit 0) normal
operation
Data path demodulator, receive
clock
Data path demodulator, receive
local oscillator
Data path demodulator, dump
signal (bit synchronized integrate
and dump processing)
The alternate uses of port 0.0 all deal with timing signals
associated with the phase shift keyed data path operation.
These signals are used for correctly setting the timing de-
lays associated with hardware dependent delays in the RF
and audio data circuitry. Applications using the WLI refer-
ence design are not required to adjust the timing settings
(register 12 contents).
Table 2. Port bit 0.1 alternate usage:
P0.1
Test Selector P0.1 Function
Reg 0x13 bits [5:4]
0
0
Follows P0.1 (Reg 7 bit 1) normal
operation
0
1
Data path demodulator, phase
shift keyed output
1
0
Data path demodulator,
integrator’s LSB
1
1
Data path demodulator, carrier
detector output
The alternate uses of port 0.1 all deal with timing signals
associated with the phase shift keyed data path operation.
These signals are used for correctly setting the timing de-
lays associated with hardware dependent delays in the RF
and audio data circuitry. Applications using the WLI refer-
ence design are not required to adjust the timing settings
(register 12 contents).
Table 3. Port bit 0.2 alternate usage:
P0.2
Reg 0x13 bit [6]
Test Selector P0.2 Function
0
Follows P0.2 (Reg 7 bit 2) normal
operation
1 Receive PN Sync Pulse
The alternate use of port 0.2 allows the receive PN gener-
ator synchronization pulse to be probed. Note that an ex-
ternal pin on the ASIC is also dedicated to this function,
and can be controlled by register 9 bits 0 and 1.
Table 4. Port bit 0.3 alternate usage:
P0.3
Test Selector P0.3 Function
Reg 0x13 bit [7]
0
Follows P0.3 (Reg 7 bit 3) normal
operation
1 Transmit PN Sync
The alternate use of port 0.3 allows the transmit PN gen-
erator synchronization pulse to be probed. Note that an
external pin on the ASIC is also dedicated to this function,
and can be controlled by register 9 bits 0 and 1.
2-11
11 Page | ||
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