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AT49BV008AT-12TI 데이터시트 PDF




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부품번호 AT49BV008AT-12TI 기능
기능 8-Megabit 1M x 8/ 512K x 16 CMOS Flash Memory
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AT49BV008AT-12TI 데이터시트, 핀배열, 회로
Features
2.7V to 3.6V Read/Write Operation
Fast Read Access Time - 120 ns
Internal Erase/Program Control
Sector Architecture
– One 8K Words (16K bytes) Boot Block with Programming Lockout
– Two 4K Words (8K bytes) Parameter Blocks
– One 496K Words (992K bytes) Main Memory Array Block
Fast Sector Erase Time - 10 seconds
Byte-by-Byte or Word-By-Word Programming - 30 µs Typical
Hardware Data Protection
DATA Polling For End Of Program Detection
Low-Power Dissipation
– 25 mA Active Current
– 50 µA CMOS Standby Current
Typical 10,000 Write Cycles
Description
The AT49BV008A(T) and AT49BV8192A(T) are 3-volt, 8-megabit Flash Memories
organized as 1,048,576 words of 8 bits each or 512K words of 16 bits each. Manufac-
tured with Atmel’s advanced nonvolatile CMOS technology, the devices offer access
times to 120 ns with power dissipation of just 67 mW at 2.7V read. When deselected,
the CMOS standby current is less than 50 µA.
The device contains a user-enabled “boot block” protection feature. Two versions of
the feature are available: the AT49BV008A/8192A locates the boot block at lowest
order addresses (“bottom boot”); the AT49BV008AT/8192AT locates it at highest
order addresses (“top boot”).
To allow for simple in-system reprogrammability, the AT49BV008A(T)/8192A(T) does
not require high input voltages for programming. Reading data out of the device is
similar to reading from an EPROM; it has standard CE, OE, and WE inputs to avoid
bus contention. Reprogramming the AT49BV008A(T)/8192A(T) is performed by first
erasing a block of data and then programming on a byte-by-byte or word-by-word
basis.
(continued)
Pin Configurations
Pin Name
A0 - A18
CE
OE
WE
RESET
RDY/BUSY
VPP
I/O0 - I/O14
I/O15 (A-1)
BYTE
NC
Function
Addresses
Chip Enable
Output Enable
Write Enable
Reset
Ready/Busy Output
Optional Power Supply for Faster
Program/Erase Operations
Data Inputs/Outputs
I/O15 (Data Input/Output, Word Mode)
A-1 (LSB Address Input, Byte Mode)
Selects Byte or Word Mode
No Connect
8-Megabit
(1M x 8/
512K x 16)
CMOS Flash
Memory
AT49BV008A
AT49BV008AT
AT49BV8192A
AT49BV8192AT
Preliminary
Rev. 1049C–09/98
1




AT49BV008AT-12TI pdf, 반도체, 판매, 대치품
device is in its standard operating mode. A low level on the
RESET input halts the present device operation and puts
the outputs of the device in a high impedance state. When
a high level is reasserted on the RESET pin, the device
returns to the Read or Standby mode, depending upon the
state of the control inputs. By applying a 12V ± 0.5V input
signal to the RESET pin the boot block array can be repro-
grammed even if the boot block program lockout feature
has been enabled (see Boot Block Programming Lockout
Override section).
ERASURE: Before a byte or word can be reprogrammed, it
must be erased. The erased state of memory bits is a logi-
cal “1”. The entire device can be erased by using the Chip
Erase command or individual sectors can be erased by
using the Sector Erase commands.
CHIP ERASE: The entire device can be erased at one time
by using the 6-byte chip erase software code. After the chip
erase has been initiated, the device will internally time the
erase operation so that no external clocks are required.
The maximum time to erase the chip is tEC.
If the boot block lockout has been enabled, the Chip Erase
will not erase the data in the boot block; it will erase the
main memory block and the parameter blocks only. After
the chip erase, the device will return to the read or standby
mode.
SECTOR ERASE: As an alternative to a full chip erase, the
device is organized into four sectors that can be individually
erased. There are two 4K word parameter block sections,
one boot block, and the main memory array block. The
Sector Erase command is a six bus cycle operation. The
sector address is latched on the falling WE edge of the
sixth cycle while the 30H data input command is latched at
the rising edge of WE. The sector erase starts after the ris-
ing edge of WE of the sixth cycle. The erase operation is
internally controlled; it will automatically time to completion.
Whenever the main memory block is erased and repro-
grammed, the two parameter blocks should be erased and
reprogrammed before the main memory block is erased
again. Whenever a parameter block is erased and repro-
grammed, the other parameter block should be erased and
reprogrammed before the first parameter block is erased
again.
BYTE/WORD PROGRAMMING: Once a memory block is
erased, it is programmed (to a logical “0”) on a byte-by-byte
or word-by-word basis. Programming is accomplished via
the internal device command register and is a 4 bus cycle
operation. The device will automatically generate the
required internal program pulses.
Any commands written to the chip during the embedded
programming cycle will be ignored. If a hardware reset hap-
pens during programming, the data at the location being
programmed will be corrupted. Please note that a data “0”
cannot be programmed back to a “1”; only erase operations
can convert “0”s to “1”s. Programming is completed after
the specified tBP cycle time. The DATA polling feature may
also be used to indicate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
size of the block is 8K words. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enabling the lockout feature will allow the boot
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be acti-
vated; the boot block’s usage as a write protected region is
optional to the user. The address range of the boot block is
00000H to 03FFFH for the AT49BV008A; FC000H to
FFFFFH for the AT49BV008AT; 00000H to 01FFFH for the
AT49BV8192A; and 7E000H to 7FFFFH for the
AT49BV8192AT.
Once the feature is enabled, the data in the boot block can
no longer be erased or programmed when input levels of
5.5V or less are used. Data in the main memory block can
still be changed through the regular programming method.
To activate the lockout feature, a series of six program
commands to specific addresses with specific data must be
performed. Please refer to the Command Definitions table.
BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the boot
block section is locked out. When the device is in the soft-
ware product identification mode (see Software Product
Identification Entry and Exit sections) a read from the fol-
lowing address location will show if programming the boot
block is locked out—00002H for the AT49BV008A and
AT49BV8192A; FC002H for the AT49BV008AT; and
7E002H for the AT49BV8192AT. If the data on I/O0 is low,
the boot block can be programmed; if the data on I/O0 is
high, the program lockout feature has been enabled and
the block cannot be programmed. The software product
identification exit code should be used to return to standard
operation.
BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE:
The user can override the boot block programming lockout
by taking the RESET pin to 12 volts during the entire chip
erase, sector erase or word programming operation. When
the RESET pin is brought back to TTL levels the boot block
programming lockout feature is again active.
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product.
4 AT49BV008A(T)/8192A(T)

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AT49BV008AT-12TI 전자부품, 판매, 대치품
AT49BV008A(T)/8192A(T)
Command Definition (in Hex) for Alternate Pin Definition of AT49BV008A(T)(1)
Command
Sequence
Bus
Cycles
1st Bus
Cycle
Addr Data
2nd Bus
Cycle
Addr Data
3rd Bus
Cycle
Addr Data
4th Bus
Cycle
Addr Data
5th Bus
Cycle
Addr Data
6th Bus
Cycle
Addr Data
Read
Chip Erase
Sector Erase
1 Addr DOUT
6 A555 AA 5AAA 55 A555 80 2555 AA 5AAA 55 A555 10
6 A555 AA 5AAA 55 A555 80 2555 AA 5AAA 55 SA(4) 30
Byte/Word Program
4 A555 AA 5AAA 55 A555 A0 Addr DIN
Boot Block Lockout(2) 6 A555 AA 5AAA 55 A555 80 2555 AA 5AAA 55 A555 40
Product ID Entry
3 A555 AA 5AAA 55 A555 90
Product ID Exit(3)
3 A555 AA 5AAA 55 A555 F0
Product ID Exit(3)
1 xxxx F0
Notes:
1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)
The ADDRESS FORMAT in each bus cycle is as follows: A15 - A0 (Hex), A-1, and A15 - A18 (Don’t Care)
2. The boot sector has the address range 00000H to 03FFFH for the AT49BV008A; FC000H to FFFFFH for the
AT49BV008AT; 00000H to 01FFFH for the AT49BV8192A; and 7E000H to 7FFFFH for the AT49BV8192AT.
3. Either one of the Product ID Exit commands can be used.
4. SA = sector addresses: (A0 - A18)
For the AT49BV008A/8192A
SA = 02XXX for BOOT BLOCK
SA = 04XXX for PARAMETER BLOCK 1
SA = 06XXX for PARAMETER BLOCK 2
SA = FEXXX for MAIN MEMORY ARRAY
For the AT49BV008AT/8192AT
SA = FEXXX for BOOT BLOCK
SA = FAXXX for PARAMETER BLOCK 1
SA = 78XXX for PARAMETER BLOCK 2
SA = 76XXX for MAIN MEMORY ARRAY
Absolute Maximum Ratings*
Temperature Under Bias ................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
Voltage on RESET
with Respect to Ground ...................................-0.6V to +13.5V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
7

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