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PDF AT49BV1604-90UC Data sheet ( Hoja de datos )
| Número de pieza | AT49BV1604-90UC | |
| Descripción | 16-megabit (1M x 16/2M x 8) 3-volt Only Flash Memory | |
| Fabricantes | ATMEL Corporation | |
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Features
• 2.7V to 3.3V Read/Write
• Access Time - 90 ns
• Sector Erase Architecture
– Thirty 32K Word (64K Byte) Sectors with Individual Write Lockout
– Eight 4K Word (8K Byte) Sectors with Individual Write Lockout
– Two 16K Word (32K Byte) Sectors with Individual Write Lockout
• Fast Word Program Time - 20 µs
• Fast Sector Erase Time - 200 ms
• Dual Plane Organization, Permitting Concurrent Read while Program/Erase
Memory Plane A: Eight 4K Word, Two 16K Word and Six 32K Word Sectors
Memory Plane B: Twenty-four 32K Word Sectors
• Erase Suspend Capability
– Supports Reading/Programming Data from Any Sector by Suspending Erase of
Any Different Sector
• Low-power Operation
– 25 mA Active
– 10 µA Standby
• Data Polling, Toggle Bit, Ready/Busy for End of Program Detection
• Optional VPP Pin for Fast Programming
• RESET Input for Device Initialization
• Sector Program Unlock Command
• TSOP, CBGA, and µBGA Package Options
• Top or Bottom Boot Block Configuration Available
Description
The AT49BV16X4(T) is 2.7- to 3.3-volt 16-megabit Flash memory organized as
1,048,576 words of 16 bits each or 2,097,152 bytes of 8 bits each. The x16 data
appears on I/O0 - I/O15; the x8 data appears on I/O0 - I/O7. The memory is divided
into 40 sectors for erase operations. The device is offered in 48-pin TSOP and 48-ball
µBGA packages. The device has CE, and OE control signals to avoid any bus
(continued)
Pin Configurations
Pin Name
A0 - A19
CE
OE
WE
RESET
RDY/BUSY
VPP
I/O0 - I/O14
I/O15 (A-1)
BYTE
NC
VCCQ
DC
Function
Addresses
Chip Enable
Output Enable
Write Enable
Reset
READY/BUSY Output
Optional Power Supply for Faster
Program/Erase Operations
Data Inputs/Outputs
I/O15 (Data Input/Output, Word Mode)
A-1 (LSB Address Input, Byte Mode)
Selects Byte or Word Mode
No Connect
Output Power Supply
Don’t Connect
16-megabit
(1M x 16/2M x 8)
3-volt Only
Flash Memory
AT49BV1604
AT49BV1604T
AT49BV1614
AT49BV1614T
Rev. 0925H–08/99
1
1 page  
AT49BV1604(T)/1614(T)
suspend feature while erasing a sector when you want to
read data from a sector in the other plane. After the erase
suspend command is given, the device requires a maxi-
mum time of 15 µs to suspend the erase operation. After
the erase operation has been suspended, the plane which
contains the suspended sector enters the erase-suspend-
read mode. The system can then read data or program
data to any other sector within the device. An address is
not required during the erase suspend command. During a
sector erase suspend, another sector cannot be erased. To
resume the sector erase operation, the system must write
the erase resume command. The erase resume command
is a one bus cycle command, which does require the plane
address (determined by A18 and A19). The device also
supports an erase suspend during a complete chip erase.
While the chip erase is suspended, the user can read from
any sector within the memory that is protected. The com-
mand sequence for a chip erase suspend and a sector
erase suspend are the same.
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING: The AT49BV16X4(T) features DATA
polling to indicate the end of a program cycle. During a pro-
gram cycle an attempted read of the last byte/word loaded
will result in the complement of the loaded data on I/O7.
Once the program cycle has been completed, true data is
valid on all outputs and the next cycle may begin. During a
chip or sector erase operation, an attempt to read the
device will give a “0” on I/O7. Once the program or erase
cycle has completed, true data will be read from the device.
DATA polling may begin at any time during the program
cycle. Please see “Status Bit Table” for more details.
TOGGLE BIT: In addition to DATA polling the
AT49BV16X4(T) provides another method for determining
the end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from the
same memory plane will result in I/O6 toggling between
one and zero. Once the program cycle has completed, I/O6
will stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle.
An additional toggle bit is available on I/O2 which can be
used in conjunction with the toggle bit which is available on
I/O6. While a sector is erase suspended, a read or a pro-
gram operation from the suspended sector will result in the
I/O2 bit toggling. Please see “Status Bit Table” for more
details.
RDY/BUSY: An open drain READY/BUSY output pin pro-
vides another method of detecting the end of a program or
erase operation. RDY/BUSY is actively pulled low during
the internal program and erase cycles and is released at
the completion of the cycle. The open drain connection
allows for OR-tying of several devices to the same
RDY/BUSY line.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the
AT49BV16X4(T) in the following ways: (a) VCC sense: if
VCC is below 1.8V (typical), the program function is inhib-
ited. (b) VCC power on delay: once VCC has reached the
VCC sense level, the device will automatically time out 10
ms (typical) before programming. (c) Program inhibit: hold-
ing any one of OE low, CE high or WE high inhibits
program cycles. (d) Noise filter: pulses of less than 15 ns
(typical) on the WE or CE inputs will not initiate a program
cycle.
INPUT LEVELS: While operating with a 2.7V to 3.6V
power supply, the address inputs and control inputs (OE,
CE, and WE) may be driven from 0 to 5.5V without
adversely affecting the operation of the device. The I/O
lines can only be driven from 0 to VCC + 0.6V.
OUTPUT LEVELS: For the 49BV1604(T), Output High
Levels (VOH) are equal to VCCQ - 0.2V (not VCC). For 2.7V -
3.6V output levels, VCCQ must be tied to VCC. For 1.8V -
2.2V output levels, VCCQ must be regulated to 2.0V ± 10%
while VCC must be regulated to 2.7V - 3.0V (for minimum
power).
5
5 Page 
AT49BV1604(T)/1614(T)
AC Byte/Word Load Characteristics
Symbol
tAS, tOES
tAH
tCS
tCH
tWP
tDS
tDH, tOEH
tWPH
Parameter
Address, OE Set-up Time
Address Hold Time
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Set-up Time
Data, OE Hold Time
Write Pulse Width High
AC Byte/Word Load Waveforms
WE Controlled
Min Max
10
100
0
0
100
100
10
50
Units
ns
ns
ns
ns
ns
ns
ns
ns
CE Controlled
11
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| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet AT49BV1604-90UC.PDF ] | |
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