AT49BV160C-70TI Datasheet PDF - ATMEL Corporation
| Part Number | AT49BV160C-70TI | |
| Description | 16-megabit (1M x 16) 3-volt Only Flash Memory | |
| Manufacturers | ATMEL Corporation | |
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Features
• Single Voltage Read/Write Operation: 2.65V to 3.6V
• Access Time – 70 ns
• Sector Erase Architecture
– Thirty-one 32K Word (64K Bytes) Sectors with Individual Write Lockout
– Eight 4K Word (8K Bytes) Sectors with Individual Write Lockout
• Fast Word Program Time – 12 µs
• Fast Sector Erase Time – 300 ms
• Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming from Any Sector by Suspending Erase
of a Different Sector
– Supports Reading Any Word by Suspending Programming of Any Other Word
• Low-power Operation
– 12 mA Active
– 13 µA Standby
• VPP Pin for Write Protection
• WP Pin for Sector Protection
• RESET Input for Device Initialization
• Flexible Sector Protection
• TSOP and CBGA Package Options
• Top or Bottom Boot Block Configuration Available
• 128-bit Protection Register
• Minimum 100,000 Erase Cycles
• Common Flash Interface (CFI)
Description
The AT49BV160C(T) is a 2.7-volt 16-megabit Flash memory organized as 1,048,576
words of 16 bits each. The memory is divided into 39 sectors for erase operations.
The device is offered in a 48-lead TSOP and a 46-ball CBGA package. The device has
CE and OE control signals to avoid any bus contention. This device can be read or
reprogrammed using a single power supply, making it ideally suited for in-system
programming.
16-megabit
(1M x 16)
3-volt Only
Flash Memory
AT49BV160C
AT49BV160CT
Pin Configurations
Pin Name
A0 - A19
CE
OE
WE
RESET
VPP
I/O0 - I/O15
NC
VCCQ
WP
Function
Addresses
Chip Enable
Output Enable
Write Enable
Reset
Write Protection
Data Inputs/Outputs
No Connect
Output Power Supply
Write Protect
3367D–FLASH–5/04
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AT49BV160C(T)
The contents of the status register [SR7:SR0] are latched on the falling edge of OE or CE
(whichever occurs last), which prevents possible bus errors that might occur if status register
contents change while being read. CE or OE must be toggled with each subsequent status
read, or the status register will not indicate completion of a Program or Erase operation.
When the Write State Machine (WSM) is active, SR7 will indicate the status of the WSM; the
remaining bits in the status register indicate whether the WSM was successful in performing
the preferred operation (see Table 1).
Table 1. Status Register Bit Definition
WSMS
ESS
ES
PS
VPPS
PSS
SLS
R
76543210
Notes
SR7 WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
Check Write State Machine bit first to determine Word Program
or Sector Erase completion, before checking program or erase
status bits.
SR6 = ERASE SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase In Progress/Completed
When Erase Suspend is issued, WSM halts execution and sets
both WSMS and ESS bits to “1” – ESS bit remains set to “1” until
an Erase Resume command is issued.
SR5 = ERASE STATUS (ES)
1 = Error in Sector Erase
0 = Successful Sector Erase
When this bit is set to “1”, WSM has applied the max number of
erase pulses to the sector and is still unable to verify successful
sector erasure.
SR4 = PROGRAM STATUS (PS)
1 = Error in Programming
0 = Successful Programming
When this bit is set to “1”, WSM has attempted but failed to
program a word
SR3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
The VPP status bit does not provide continuous indication of VPP
level. The WSM interrogates VPP level only after the Program or
Erase command sequences have been entered and informs the
system if VPP has not been switched on. The VPP is also checked
before the operation is verified by the WSM.
SR2 = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
0 = Program in Progress/Completed
When Program Suspend is issued, WSM halts execution and
sets both WSMS and PSS bits to “1”. PSS bit remains set to “1”
until a Program Resume command is issued.
SR1 = SECTOR LOCK STATUS
1 = Prog/Erase attempted on a locked sector; Operation aborted.
0 = No operation to locked sectors
If a Program or Erase operation is attempted to one of the locked
sectors, this bit is set by the WSM. The operation specified is
aborted and the device is returned to read status mode.
SR0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
This bit is reserved for future use and should be masked out
when polling the status register.
Note: 1. A Command Sequence Error is indicated when SR1, SR3, SR4 and SR5 are set.
3367D–FLASH–5/04
5
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| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
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