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AT49BV160CT-70CI 데이터시트 PDF




ATMEL Corporation에서 제조한 전자 부품 AT49BV160CT-70CI은 전자 산업 및 응용 분야에서
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부품번호 AT49BV160CT-70CI 기능
기능 16-megabit (1M x 16) 3-volt Only Flash Memory
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AT49BV160CT-70CI 데이터시트, 핀배열, 회로
Features
Single Voltage Read/Write Operation: 2.65V to 3.6V
Access Time – 70 ns
Sector Erase Architecture
– Thirty-one 32K Word (64K Bytes) Sectors with Individual Write Lockout
– Eight 4K Word (8K Bytes) Sectors with Individual Write Lockout
Fast Word Program Time – 12 µs
Fast Sector Erase Time – 300 ms
Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming from Any Sector by Suspending Erase
of a Different Sector
– Supports Reading Any Word by Suspending Programming of Any Other Word
Low-power Operation
– 12 mA Active
– 13 µA Standby
VPP Pin for Write Protection
WP Pin for Sector Protection
RESET Input for Device Initialization
Flexible Sector Protection
TSOP and CBGA Package Options
Top or Bottom Boot Block Configuration Available
128-bit Protection Register
Minimum 100,000 Erase Cycles
Common Flash Interface (CFI)
Description
The AT49BV160C(T) is a 2.7-volt 16-megabit Flash memory organized as 1,048,576
words of 16 bits each. The memory is divided into 39 sectors for erase operations.
The device is offered in a 48-lead TSOP and a 46-ball CBGA package. The device has
CE and OE control signals to avoid any bus contention. This device can be read or
reprogrammed using a single power supply, making it ideally suited for in-system
programming.
16-megabit
(1M x 16)
3-volt Only
Flash Memory
AT49BV160C
AT49BV160CT
Pin Configurations
Pin Name
A0 - A19
CE
OE
WE
RESET
VPP
I/O0 - I/O15
NC
VCCQ
WP
Function
Addresses
Chip Enable
Output Enable
Write Enable
Reset
Write Protection
Data Inputs/Outputs
No Connect
Output Power Supply
Write Protect
3367D–FLASH–5/04
1




AT49BV160CT-70CI pdf, 반도체, 판매, 대치품
Device
Operation
READ: When the AT49BV160C(T) is in the read mode, with CE and OE low and WE high, the
data stored at the memory location determined by the address pins are asserted on the out-
puts. The outputs are put in the high impedance state whenever CE or OE is high. This dual-
line control gives designers flexibility in preventing bus contention.
COMMAND SEQUENCES: When the device is first powered on, it will be in the read mode. In
order to perform other device functions, a series of command sequences are entered into the
device. The command sequences are shown in the “Command Definition” table on page 15
(I/O8 - I/O15 are don’t care inputs for the command codes). The command sequences are
written by applying a low pulse on the WE or CE input with CE or WE low (respectively) and
OE high. The address and data are latched by the first rising edge of CE or WE. Standard
microprocessor write timings are used. The address locations used in the command
sequences are not affected by entering the command sequences.
RESET: A RESET input pin is provided to ease some system applications. When RESET is at
a logic high level, the device is in its standard operating mode. A low level on the RESET input
halts the present device operation and puts the outputs of the device in a high impedance
state. When a high level is reasserted on the RESET pin, the device returns to the read mode,
depending upon the state of the control inputs.
ERASURE: Before a word can be reprogrammed, it must be erased. The erased state of
memory bits is a logical “1”. The individual sectors can be erased by using the Sector Erase
command.
SECTOR ERASE: The device is organized into 39 sectors (SA0 - SA38) that can be individu-
ally erased. The Sector Erase command is a two-bus cycle operation. The sector address and
the D0H Data Input command are latched on the rising edge of WE. The sector erase starts
after the rising edge of WE of the second cycle provided the given sector has not been pro-
tected. The erase operation is internally controlled; it will automatically time to completion. The
maximum time to erase a sector is tSEC. An attempt to erase a sector that has been protected
will result in the operation terminating immediately.
WORD PROGRAMMING: Once a memory sector is erased, it is programmed (to a logical “0”)
on a word-by-word basis. Programming is accomplished via the Internal Device command reg-
ister and is a two-bus cycle operation. The device will automatically generate the required
internal program pulses.
Any commands written to the chip during the embedded programming cycle will be ignored. If
a hardware reset happens during programming, the data at the location being programmed
will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase
operations can convert “0”s to “1”s. Programming is completed after the specified tBP cycle
time. If the program status bit is a “1”, the device was not able to verify that the program oper-
ation was performed successfully. The status register indicates the programming status. While
the program sequence executes, status bit I/O7 is “0”. While programming, the only valid com-
mands are Read Status Register, Program Suspend and Program Resume.
VPP PIN: The circuitry of the AT49BV160C(T) is designed so that the device cannot be pro-
grammed or erased if the VPP voltage is less that 0.4V. When VPP is at 1.5V or above, normal
program and erase operations can be performed. The VPP pin cannot be left floating.
READ STATUS REGISTER: The status register indicates the status of device operations and
the success/failure of that operation. The Read Status Register command causes subsequent
reads to output data from the status register until another command is issued. To return to
reading from the memory, issue a Read command.
The status register bits are output on I/O7 - I/O0. The upper byte, I/O15 - I/O8, outputs 00H
when a Read Status Register command is issued.
4 AT49BV160C(T)
3367D–FLASH–5/04

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AT49BV160CT-70CI 전자부품, 판매, 대치품
AT49BV160C(T)
Table 2. Hardlock and Softlock Protection Configurations in Conjunction with WP
VPP
VCC/5V
VCC/5V
Erase/
Hard-
Soft-
Prog
WP
lock
lock
Allowed?
Comments
000
Yes No sector is locked
001
No Sector is Softlocked. The Unlock command can
unlock the sector.
VCC/5V
011
No Hardlock protection mode is enabled. The sector
cannot be unlocked.
VCC/5V
VCC/5V
100
101
Yes No sector is locked.
No Sector is Softlocked. The Unlock command can
unlock the sector.
VCC/5V
110
Yes Hardlock protection mode is overridden and the
sector is not locked.
VCC/5V
111
No Hardlock protection mode is overridden and the
sector can be unlocked via the Unlock command.
VIL
xxx
No Erase and Program Operations cannot be
performed.
Figure 1. Sector Locking State Diagram
UNLOCKED
LOCKED
WP = VIL = 0
[000]
60h/
D0h
60h/2Fh
60h/01h
[001]
60h/
2Fh
Power-Up/Reset
Default
[011]
Hardlocked
WP = VIH = 1
[110]
[100]
60h/D0h
60h/
D0h
60h/
01h
[111]
Hardlocked is disabled by
WP = VIH
60h/
2Fh
60h/
01h
60h/
2Fh
Power-Up/Reset
Default
[101]
60h/D0h = Unlock Command
60h/01h = Softlock Command
60h/2Fh = Hardlock Command
Notes: 1. The notation [X, Y, Z] denotes the locking state of a sector. The current locking state of a sector is defined by the state of WP
and the two bits of the sector-lock status D[1:0].
3367D–FLASH–5/04
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부품번호상세설명 및 기능제조사
AT49BV160CT-70CI

16-megabit (1M x 16) 3-volt Only Flash Memory

ATMEL Corporation
ATMEL Corporation

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