AT49BV162AT-70CI Datasheet PDF - ATMEL Corporation
| Part Number | AT49BV162AT-70CI | |
| Description | 16-megabit (1M x 16/2M x 8) 3-volt Only Flash Memory | |
| Manufacturers | ATMEL Corporation | |
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Features
• Single Voltage Read/Write Operation: 2.65V to 3.6V
• Access Time – 70 ns
• Sector Erase Architecture
– Thirty-one 32K Word (64K Bytes) Sectors with Individual Write Lockout
– Eight 4K Word (8K Bytes) Sectors with Individual Write Lockout
• Fast Word Program Time – 12 µs
• Fast Sector Erase Time – 300 ms
• Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming from Any Sector by Suspending Erase
of a Different Sector
– Supports Reading Any Byte/Word in the Non-suspending Sectors by Suspending
Programming of Any Other Byte/Word
• Low-power Operation
– 12 mA Active
– 13 µA Standby
• Data Polling, Toggle Bit, Ready/Busy for End of Program Detection
• VPP Pin for Write Protection
• RESET Input for Device Initialization
• Sector Lockdown Support
• TSOP and CBGA Package Options
• Top or Bottom Boot Block Configuration Available
• 128-bit Protection Register
• Minimum 100,000 Erase Cycles
• Common Flash Interface (CFI)
Description
The AT49BV162A(T)/163A(T) is a 2.7-volt 16-megabit Flash memory organized as
1,048,576 words of 16 bits each or 2,097,152 bytes of 8 bits each. The x16 data
appears on I/O0 - I/O15; the x8 data appears on I/O0 - I/O7. The memory is divided
into 71 sectors for erase operations. The device is offered in a 48-lead TSOP and a
48-ball CBGA package. The device has CE and OE control signals to avoid any bus
contention. This device can be read or reprogrammed using a single power supply,
making it ideally suited for in-system programming.
Pin Configurations
Pin Name
Function
A0 - A19
Addresses
CE Chip Enable
OE Output Enable
WE Write Enable
RESET
Reset
RDY/BUSY
READY/BUSY Output
VPP(1)
Write Protection
I/O0 - I/O14
Data Inputs/Outputs
I/O15 (A-1)
I/O15 (Data Input/Output, Word Mode)
A-1 (LSB Address Input, Byte Mode)
BYTE
Selects Byte or Word Mode
NC No Connect
Note: 1. The VPP pin is not available for the AT49BV163A(T).
16-megabit
(1M x 16/2M x 8)
3-volt Only
Flash Memory
AT49BV162A
AT49BV162AT
AT49BV163A
AT49BV163AT
3349G–FLASH–7/04
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AT49BV162/163A(T)
Any commands written to the chip during the embedded programming cycle will be ignored. If
a hardware reset happens during programming, the data at the location being programmed
will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase
operations can convert “0”s to “1”s. Programming is completed after the specified tBP cycle
time. The Data Polling feature or the Toggle Bit feature may be used to indicate the end of a
program cycle. If the erase/program status bit is a “1”, the device was not able to verify that the
erase or program operation was performed successfully.
VPP PIN: The circuitry of the AT49BV162A(T) is designed so that the device cannot be pro-
grammed or erased if the VPP voltage is less that 0.4V. When VPP is at 0.9V or above, normal
program and erase operations can be performed. The VPP pin cannot be left floating.
PROGRAM/ERASE STATUS: The device provides several bits to determine the status of a
program or erase operation: I/O2, I/O3, I/O5, I/O6 and I/O7. The “Status Bit Table” on page 11
and the following four sections describe the function of these bits. To provide greater flexibility
for system designers, the AT49BV162A(T)/163A(T) contains a programmable configuration
register. The configuration register allows the user to specify the status bit operation. The con-
figuration register can be set to one of two different values, “00” or “01”. If the configuration
register is set to “00”, the part will automatically return to the read mode after a successful pro-
gram or erase operation. If the configuration register is set to a “01”, a Product ID Exit
command must be given after a successful program or erase operation before the part will
return to the read mode. It is important to note that whether the configuration register is set to
a “00” or to a “01”, any unsuccessful program or erase operation requires using the Product ID
Exit command to return the device to read mode. The default value (after power-up) for the
configuration register is “00”. Using the four-bus cycle Set Configuration Register command as
shown in the “Command Definition in Hex” table on page 12, the value of the configuration
register can be changed. Voltages applied to the RESET pin will not alter the value of the con-
figuration register. The value of the configuration register will affect the operation of the I/O7
status bit as described below.
DATA POLLING: The AT49BV162A(T)/163A(T) features Data Polling to indicate the end of a
program cycle. If the status configuration register is set to a “00”, during a program cycle an
attempted read of the last byte/word loaded will result in the complement of the loaded data on
I/O7. Once the program cycle has been completed, true data is valid on all outputs and the
next cycle may begin. During a chip or sector erase operation, an attempt to read the device
will give a “0” on I/O7. Once the program or erase cycle has completed, true data will be read
from the device. Data Polling may begin at any time during the program cycle. Please see
“Status Bit Table” on page 11 for more details.
If the status bit configuration register is set to a “01”, the I/O7 status bit will be low while the
device is actively programming or erasing data. I/O7 will go high when the device has com-
pleted a program or erase operation. Once I/O7 has gone high, status information on the other
pins can be checked.
The Data Polling status bit must be used in conjunction with the erase/program and VPP status
bit as shown in the algorithm in Figures 1 and 2 on page 9.
3349G–FLASH–7/04
5
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| Information | Total 29 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
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