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PDF AT49BV322AT-70CI Data sheet ( Hoja de datos )
| Número de pieza | AT49BV322AT-70CI | |
| Descripción | 32-megabit (2M x 16/4M x 8) 3-volt Only Flash Memory | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Single Voltage Read/Write Operation: 2.65V to 3.6V
• Access Time – 70 ns
• Sector Erase Architecture
– Sixty-three 32K Word (64K Bytes) Sectors with Individual Write Lockout
– Eight 4K Word (8K Bytes) Sectors with Individual Write Lockout
• Fast Word Program Time – 12 µs
• Fast Sector Erase Time – 300 ms
• Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming from Any Sector by Suspending Erase
of a Different Sector
– Supports Reading Any Byte/Word in the Non-suspending Sectors by Suspending
Programming of Any Other Byte/Word
• Low-power Operation
– 12 mA Active
– 13 µA Standby
• Data Polling, Toggle Bit, Ready/Busy for End of Program Detection
• VPP Pin for Write Protection
• RESET Input for Device Initialization
• Sector Lockdown Support
• TSOP and CBGA Package Options
• Top or Bottom Boot Block Configuration Available
• 128-bit Protection Register
• Minimum 100,000 Erase Cycles
• Common Flash Interface (CFI)
32-megabit
(2M x 16/4M x 8)
3-volt Only
Flash Memory
AT49BV322A
AT49BV322AT
Description
The AT49BV322A(T) is a 2.7-volt 32-megabit Flash memory organized as 2,097,152
words of 16 bits each or 4,194,304 bytes of 8 bits each. The x16 data appears on I/O0
- I/O15; the x8 data appears on I/O0 - I/O7. The memory is divided into 71 sectors for
erase operations. The device is offered in a 48-lead TSOP and a 48-ball CBGA pack-
age. The device has CE and OE control signals to avoid any bus contention. This
device can be read or reprogrammed using a single power supply, making it ideally
suited for in-system programming.
Pin Configurations
Pin Name
A0 - A20
CE
OE
WE
RESET
RDY/BUSY
VPP
I/O0 - I/O14
I/O15 (A-1)
BYTE
NC
Function
Addresses
Chip Enable
Output Enable
Write Enable
Reset
READY/BUSY Output
Write Protection
Data Inputs/Outputs
I/O15 (Data Input/Output, Word Mode)
A-1 (LSB Address Input, Byte Mode)
Selects Byte or Word Mode
No Connect
3308H–FLASH–5/04
1
1 page  
AT49BV322A(T)
Any commands written to the chip during the embedded programming cycle will be ignored. If
a hardware reset happens during programming, the data at the location being programmed
will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase
operations can convert “0”s to “1”s. Programming is completed after the specified tBP cycle
time. The Data Polling feature or the Toggle Bit feature may be used to indicate the end of a
program cycle. If the erase/program status bit is a “1”, the device was not able to verify that the
erase or program operation was performed successfully.
VPP PIN: The circuitry of the AT49BV322A(T) is designed so that the device cannot be pro-
grammed or erased if the VPP voltage is less that 0.4V. When VPP is at 0.9V or above, normal
program and erase operations can be performed. The VPP pin cannot be left floating.
PROGRAM/ERASE STATUS: The device provides several bits to determine the status of a
program or erase operation: I/O2, I/O3, I/O5, I/O6 and I/O7. The “Status Bit Table” on page 11
and the following four sections describe the function of these bits. To provide greater flexibility
for system designers, the AT49BV322A(T) contains a programmable configuration register.
The configuration register allows the user to specify the status bit operation. The configuration
register can be set to one of two different values, “00” or “01”. If the configuration register is set
to “00”, the part will automatically return to the read mode after a successful program or erase
operation. If the configuration register is set to a “01”, a Product ID Exit command must be
given after a successful program or erase operation before the part will return to the read
mode. It is important to note that whether the configuration register is set to a “00” or to a “01”,
any unsuccessful program or erase operation requires using the Product ID Exit command to
return the device to read mode. The default value (after power-up) for the configuration regis-
ter is “00”. Using the four-bus cycle Set Configuration Register command as shown in the
“Command Definition in Hex” table on page 12, the value of the configuration register can be
changed. Voltages applied to the RESET pin will not alter the value of the configuration regis-
ter. The value of the configuration register will affect the operation of the I/O7 status bit as
described below.
DATA POLLING: The AT49BV322A(T) features Data Polling to indicate the end of a program
cycle. If the status configuration register is set to a “00”, during a program cycle an attempted
read of the last byte/word loaded will result in the complement of the loaded data on I/O7.
Once the program cycle has been completed, true data is valid on all outputs and the next
cycle may begin. During a chip or sector erase operation, an attempt to read the device will
give a “0” on I/O7. Once the program or erase cycle has completed, true data will be read from
the device. Data Polling may begin at any time during the program cycle. Please see “Status
Bit Table” on page 11 for more details.
If the status bit configuration register is set to a “01”, the I/O7 status bit will be low while the
device is actively programming or erasing data. I/O7 will go high when the device has com-
pleted a program or erase operation. Once I/O7 has gone high, status information on the other
pins can be checked.
The Data Polling status bit must be used in conjunction with the erase/program and VPP status
bit as shown in the algorithm in Figures 1 and 2 on page 9.
3308H–FLASH–5/04
5
5 Page 
AT49BV322A(T)
Status Bit Table
Status Bit
I/O7
I/O7
I/O6
I/O5(1)
I/O3(2)
I/O2 RDY/BUSY
Configuration Register
00
01
00/01
00/01
00/01
00/01
00/01
Programming
I/O7 0 TOGGLE 0 0 1 0
Erasing
0 0 TOGGLE 0 0 TOGGLE 0
Erase Suspended & Read
Erasing Sector
1
1
1
0
0 TOGGLE 1
Erase Suspended & Read
Non-erasing Sector
DATA
DATA
DATA
DATA
DATA
DATA
1
Erase Suspended &
Program Non-erasing Sector
I/O7
0 TOGGLE 0
0 TOGGLE 0
Erase Suspended &
Program Suspended and
Reading from Non-
suspended Sectors
DATA
DATA
DATA
DATA
DATA
DATA
1
Program Suspended & Read
Programming Sector
I/O7
1
1
0
0 TOGGLE 1
Program Suspended & Read
Non-programming Sector
DATA
DATA
DATA
DATA
DATA
DATA
1
Notes: 1. I/O5 switches to a “1” when a program or an erase operation has exceeded the maximum time limits or when a program or
sector erase operation is performed on a protected sector.
2. I/O3 switches to a “1” when the VPP level is not high enough to successfully perform program and erase operations.
3308H–FLASH–5/04
11
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