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AT49BV322AT-70TI 데이터시트 PDF




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부품번호 AT49BV322AT-70TI 기능
기능 32-megabit (2M x 16/4M x 8) 3-volt Only Flash Memory
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AT49BV322AT-70TI 데이터시트, 핀배열, 회로
Features
Single Voltage Read/Write Operation: 2.65V to 3.6V
Access Time – 70 ns
Sector Erase Architecture
– Sixty-three 32K Word (64K Bytes) Sectors with Individual Write Lockout
– Eight 4K Word (8K Bytes) Sectors with Individual Write Lockout
Fast Word Program Time – 12 µs
Fast Sector Erase Time – 300 ms
Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming from Any Sector by Suspending Erase
of a Different Sector
– Supports Reading Any Byte/Word in the Non-suspending Sectors by Suspending
Programming of Any Other Byte/Word
Low-power Operation
– 12 mA Active
– 13 µA Standby
Data Polling, Toggle Bit, Ready/Busy for End of Program Detection
VPP Pin for Write Protection
RESET Input for Device Initialization
Sector Lockdown Support
TSOP and CBGA Package Options
Top or Bottom Boot Block Configuration Available
128-bit Protection Register
Minimum 100,000 Erase Cycles
Common Flash Interface (CFI)
32-megabit
(2M x 16/4M x 8)
3-volt Only
Flash Memory
AT49BV322A
AT49BV322AT
Description
The AT49BV322A(T) is a 2.7-volt 32-megabit Flash memory organized as 2,097,152
words of 16 bits each or 4,194,304 bytes of 8 bits each. The x16 data appears on I/O0
- I/O15; the x8 data appears on I/O0 - I/O7. The memory is divided into 71 sectors for
erase operations. The device is offered in a 48-lead TSOP and a 48-ball CBGA pack-
age. The device has CE and OE control signals to avoid any bus contention. This
device can be read or reprogrammed using a single power supply, making it ideally
suited for in-system programming.
Pin Configurations
Pin Name
A0 - A20
CE
OE
WE
RESET
RDY/BUSY
VPP
I/O0 - I/O14
I/O15 (A-1)
BYTE
NC
Function
Addresses
Chip Enable
Output Enable
Write Enable
Reset
READY/BUSY Output
Write Protection
Data Inputs/Outputs
I/O15 (Data Input/Output, Word Mode)
A-1 (LSB Address Input, Byte Mode)
Selects Byte or Word Mode
No Connect
3308H–FLASH–5/04
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AT49BV322AT-70TI pdf, 반도체, 판매, 대치품
Device
Operation
READ: The AT49BV322A(T) is accessed like an EPROM. When CE and OE are low and WE
is high, the data stored at the memory location determined by the address pins are asserted
on the outputs. The outputs are put in the high impedance state whenever CE or OE is high.
This dual-line control gives designers flexibility in preventing bus contention.
COMMAND SEQUENCES: When the device is first powered on, it will be reset to the read or
standby mode, depending upon the state of the control line inputs. In order to perform other
device functions, a series of command sequences are entered into the device. The command
sequences are shown in the “Command Definition in Hex” table on page 12 (I/O8 - I/O15 are
don’t care inputs for the command codes). The command sequences are written by applying a
low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address
is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the
first rising edge of CE or WE. Standard microprocessor write timings are used. The address
locations used in the command sequences are not affected by entering the command
sequences.
RESET: A RESET input pin is provided to ease some system applications. When RESET is at
a logic high level, the device is in its standard operating mode. A low level on the RESET input
halts the present device operation and puts the outputs of the device in a high impedance
state. When a high level is reasserted on the RESET pin, the device returns to the read or
standby mode, depending upon the state of the control inputs.
ERASURE: Before a byte/word can be reprogrammed, it must be erased. The erased state of
memory bits is a logical “1”. The entire device can be erased by using the Chip Erase com-
mand or individual sectors can be erased by using the Sector Erase command.
CHIP ERASE: The entire device can be erased at one time by using the six-byte chip erase
software code. After the chip erase has been initiated, the device will internally time the erase
operation so that no external clocks are required. The maximum time to erase the chip is tEC.
If the sector lockdown has been enabled, the chip erase will not erase the data in the sector
that has been locked out; it will erase only the unprotected sectors. After the chip erase, the
device will return to the read or standby mode.
SECTOR ERASE: As an alternative to a full chip erase, the device is organized into 71 sec-
tors (SA0 - SA70) that can be individually erased. The Sector Erase command is a six-bus
cycle operation. The sector address is latched on the falling WE edge of the sixth cycle while
the 30H data input command is latched on the rising edge of WE. The sector erase starts after
the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will
automatically time to completion. The maximum time to erase a sector is tSEC. When the sec-
tor programming lockdown feature is not enabled, the sector will erase (from the same Sector
Erase command). An attempt to erase a sector that has been protected will result in the oper-
ation terminating immediately.
BYTE/WORD PROGRAMMING: Once a memory block is erased, it is programmed (to a logi-
cal “0”) on a byte-by-byte or on a word-by-word basis. Programming is accomplished via the
internal device command register and is a four-bus cycle operation. The device will automati-
cally generate the required internal program pulses.
4 AT49BV322A(T)
3308H–FLASH–5/04

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AT49BV322AT-70TI 전자부품, 판매, 대치품
AT49BV322A(T)
SECTOR LOCKDOWN OVERRIDE: The only way to unlock a sector that is locked down is
through reset or power-up cycles. After power-up or reset, the content of a sector that is
locked down can be erased and reprogrammed.
ERASE SUSPEND/ERASE RESUME: The Erase Suspend command allows the system to
interrupt a sector or chip erase operation and then program or read data from a different sector
within the memory. After the Erase Suspend command is given, the device requires a maxi-
mum time of 15 µs to suspend the erase operation. After the erase operation has been
suspended, the system can then read data or program data to any other sector within the
device. An address is not required during the Erase Suspend command. During a sector erase
suspend, another sector cannot be erased. To resume the sector erase operation, the system
must write the Erase Resume command. The Erase Resume command is a one-bus cycle
command. The device also supports an erase suspend during a complete chip erase. While
the chip erase is suspended, the user can read from any sector within the memory that is pro-
tected. The command sequence for a chip erase suspend and a sector erase suspend are the
same.
PROGRAM SUSPEND/PROGRAM RESUME: The Program Suspend command allows the
system to interrupt a programming operation and then read data from a different byte/word
within the memory. After the Program Suspend command is given, the device requires a max-
imum of 20 µs to suspend the programming operation. After the programming operation has
been suspended, the system can then read data from any other byte/word that is not con-
tained in the sector in which the programming operation was suspended. An address is not
required during the program suspend operation. To resume the programming operation, the
system must write the Program Resume command. The program suspend and resume are
one-bus cycle commands. The command sequence for the erase suspend and program sus-
pend are the same, and the command sequence for the erase resume and program resume
are the same.
PRODUCT IDENTIFICATION: The product identification mode identifies the device and man-
ufacturer as Atmel. It is accessed using a software operation.
For details, see “Operating Modes” on page 18 or “Software Product Identification Entry/Exit”
sections on page 25.
128-BIT PROTECTION REGISTER: The AT49BV322A(T) contains a 128-bit register that can
be used for security purposes in system design. The protection register is divided into two 64-
bit blocks. The two blocks are designated as block A and block B. The data in block A is
non-changeable and is programmed at the factory with a unique number. The data in block B
is programmed by the user and can be locked out such that data in the block cannot be repro-
grammed. To program block B in the protection register, the four-bus cycle Program
Protection Register command must be used as shown in the “Command Definition in Hex”
table on page 12. To lock out block B, the four-bus cycle Lock Protection Register command
must be used as shown in the “Command Definition in Hex” table. Data bit D1 must be zero
during the fourth bus cycle. All other data bits during the fourth bus cycle are don’t cares. To
determine whether block B is locked out, the Product ID Entry command is given followed by a
read operation from address 80H. If data bit D1 is zero, block B is locked. If data bit D1 is one,
block B can be reprogrammed. Please see the “Protection Register Addressing Table” on
page 13 for the address locations in the protection register. To read the protection register, the
Product ID Entry command is given followed by a normal read operation from an address
within the protection register. After determining whether block B is protected or not, or reading
the protection register, the Product ID Exit command must be given prior to performing any
other operation.
3308H–FLASH–5/04
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부품번호상세설명 및 기능제조사
AT49BV322AT-70TI

32-megabit (2M x 16/4M x 8) 3-volt Only Flash Memory

ATMEL Corporation
ATMEL Corporation

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