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AT49BV8192T-20TC 데이터시트 PDF




ATMEL Corporation에서 제조한 전자 부품 AT49BV8192T-20TC은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 AT49BV8192T-20TC 자료 제공

부품번호 AT49BV8192T-20TC 기능
기능 8-Megabit 512K x 16 CMOS Flash Memory
제조업체 ATMEL Corporation
로고 ATMEL Corporation 로고


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AT49BV8192T-20TC 데이터시트, 핀배열, 회로
Features
Low Voltage Operation
– 2.7V Read
– 5V Program/Erase
Fast Read Access Time - 120 ns
Internal Erase/Program Control
Sector Architecture
– One 8K Words (16K bytes) Boot Block with Programming Lockout
– Two 8K Words (16K bytes) Parameter Blocks
– One 488K Words (976K bytes) Main Memory Array Block
Fast Sector Erase Time - 10 seconds
Word-By-Word Programming - 30 µs/Word
Hardware Data Protection
DATA Polling For End Of Program Detection
Low Power Dissipation
– 25 mA Active Current
– 50 µA CMOS Standby Current
Typical 10,000 Write Cycles
Description
The AT49BV8192 and AT49LV8192 are 3-volt, 8-megabit Flash Memories organized
as 512K words of 16 bits each. Manufactured with Atmel’s advanced nonvolatile
CMOS technology, the devices offer access times to 120 ns with power dissipation of
just 67 mW at 2.7V read. When deselected, the CMOS standby current is less than 50
µA. (continued)
Pin Configurations
Pin Name
Function
A0 - A18
Addresses
CE Chip Enable
OE Output Enable
WE Write Enable
RESET
Reset
VPP
Program/Erase Power
Supply
I/O0 - I/O15
Data
Inputs/Outputs
NC No Connect
TSOP Top View
Type 1
A15
A14
A13
A12
A11
A10
A9
A8
NC
WE NC
RESET
VPP NC
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
14 13
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
NC
GND
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
GND
CE
A0
SOIC (SOP)
VPP
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
GND
OE
I/O0
I/O8
I/O1
I/O9
I/O2
I/O10
I/O3
I/O11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 RESET
43 WE
42 A8
41 A9
40 A10
39 A11
38 A12
37 A13
36 A14
35 A15
34 A16
33 NC
32 GND
31 I/O15
30 I/O7
29 I/O14
28 I/O6
27 I/O13
26 I/O5
25 I/O12
24 I/O4
23 VCC
8-Megabit
(512K x 16)
CMOS Flash
Memory
AT49BV8192
AT49BV8192T
AT49LV8192
AT49LV8192T
0978B-A–11/97
1




AT49BV8192T-20TC pdf, 반도체, 판매, 대치품
TOGGLE BIT: In addition to DATA polling the
AT49BV/LV8192 provides another method for determining
the end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from the
device will result in I/O6 toggling between one and zero.
Once the program cycle has completed, I/O6 will stop tog-
gling and valid data will be read. Examining the toggle bit
may begin at any time during a program cycle.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the
AT49BV/LV8192 in the following ways: (a) VCC sense: if
VCC is below 1.8V (typical), the program function is inhib-
ited. (b) VCC power on delay: once VCC has reached the
VCC sense level, the device will automatically time out 10
ms (typical) before programming. (c) Program inhibit: hold-
ing any one of OE low, CE high or WE high inhibits pro-
gram cycles. (d) Noise filter: pulses of less than 15 ns (typi-
cal) on the WE or CE inputs will not initiate a program
cycle.
INPUT LEVELS: While operating with a 2.7V to 3.6V
power supply, the address inputs and control inputs (OE,
CE, and WE) may be driven from 0 to 5.5V without
adversely affecting the operation of the device. The I/O
lines can only be driven from 0 to VCC + 0.6V.
4 AT49BV/LV8192(T)

4페이지










AT49BV8192T-20TC 전자부품, 판매, 대치품
AT49BV/LV8192(T)
AC Read Characteristics
Symbol
tACC
tCE(1)
tOE(2)
tDF(3)(4)
tOH
Parameter
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE to Output Float
Output Hold from OE, CE
or Address, whichever occurred first
AC Read Waveforms(1)(2)(3)(4)
AT49BV/LV8192-12
Min Max
120
120
0 50
0 30
AT49BV/LV8192-15
Min Max
150
150
0 100
0 50
AT49BV/LV8192-20
Min Max
200
200
0 100
0 50
Units
ns
ns
ns
ns
0 0 0 ns
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and Measurement Level
Output Test Load
tR, tF < 5 ns
Pin Capacitance
(f = 1 Mhz, T = 25°C)(1)
Typ Max
CIN
COUT
Note:
46
8 12
1. This parameter is characterized and is not 100% tested.
Units
pF
pF
Conditions
VIN = 0V
VOUT = 0V
7

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