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PDF AT49LH004 Data sheet ( Hoja de datos )
| Número de pieza | AT49LH004 | |
| Descripción | 4-megabit Firmware Hub and Low-Pin Count Flash Memory | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Complies with Intel® Low-Pin Count (LPC) Interface Specification Revision 1.1
– Supports both Firmware Hub (FWH) and LPC Memory Read and Write Cycles
• Auto-detection of FWH and LPC Memory Cycles
– Can Be Used as FWH for Intel 8xx, E7xxx, and E8xxx Series Chipsets
– Can Be Used as LPC Flash for Non-Intel Chipsets
• Flexible, Optimized Sectoring for BIOS Applications
– 16-Kbyte Top Boot Sector, Two 8-Kbyte Sectors, One 32-Kbyte Sector,
Three 64-Kbyte Sectors
– Or Memory Array Can Be Divided Into Four Uniform 64-Kbyte Sectors for Erasing
• Two Configurable Interfaces
– FWH/LPC Interface for In-System Operation
– Address/Address Multiplexed (A/A Mux) Interface for Programming during
Manufacturing
• FWH/LPC Interface
– Operates with the 33 MHz PCI Bus Clock
– 5-signal Communication Interface Supporting Byte Reads and Writes
– Two Hardware Write Protect Pins: TBL for Top Boot Sector and WP for All
Other Sectors
– Five General-purpose Input (GPI) Pins for System Design Flexibility
– Identification (ID) Pins for Multiple Device Selection
– Sector Locking Registers for Individual Sector Read and Write Protection
• A/A Mux Interface
– 11-pin Multiplexed Address and 8-pin Data Interface
– Facilitates Fast In-System or Out-of-System Programming
• Single Voltage Operation
– 3.0V to 3.6V Supply Voltage for Read and Write Operations
• Industry-Standard Package Options
– 32-lead PLCC
– 40-lead TSOP
2-megabit
Firmware Hub
and Low-Pin
Count Flash
Memory
AT49LH002
Description
The AT49LH002 is a Flash memory device designed for use in PC and notebook BIOS
applications. The device complies with version 1.1 of Intel’s LPC Interface Specifica-
tion, providing support for both FWH and LPC memory read and write cycles. The
device can also automatically detect the memory cycle type to allow the AT49LH002
to be used as a FWH with Intel chipsets or as an LPC Flash with non-Intel chipsets.
Pin Configurations
PLCC
TSOP
[A7] GPI1
[A6] GPI0
[A5] WP
[A4] TBL
[A3] ID3
[A2] ID2
[A1] ID1
[A0] ID0
[I/O0] FWH0/LAD0
5
6
7
8
9
10
11
12
13
29 IC [IC]
28 GND
27 NC
26 NC
25 VCC
24 INIT [OE]
23 FWH4/LFRAME [WE]
22 RES [RDY/BSY]
21 RES [I/O7]
NC
[IC] IC
NC
NC
NC
NC
[A10] GPI4
NC
[R/C] CLK
VCC
NC
[RST] RST
NC
NC
[A9] GPI3
[A8] GPI2
[A7] GPI1
[A6] GPI0
[A5] WP
[A4] TBL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 GND
39 VCC
38 FWH4/LFRAME [WE]
37 INIT [OE]
36 RES [RDY/BSY]
35 RES [I/O7]
34 RES [I/O6]
33 RES [I/O5]
32 RES [I/O4]
31 VCC
30 GND
29 GND
28 FWH3/LAD3 [I/O3]
27 FWH2/LAD2 [I/O2]
26 FWH1/LAD1 [I/O1]
25 FWH0/LAD0 [I/O0]
24 ID0 [A0]
23 ID1 [A1]
22 ID2 [A2]
21 ID3 [A3]
Note: [ ] Designates A/A Mux Interface.
3377B–FLASH–9/03
1
1 page  
AT49LH002
Table 1. Signal Descriptions (Continued)
Symbol
I/O[7:0]
R/C
OE
WE
RDY/BSY
VCC
GND
NC
RES
Name and Function
DATA INPUTS/OUTPUTS: The I/O pins are used in the A/A Mux interface to input
data and commands during write cycles and to output data during memory array,
Status Register, and identifier code read cycles. Data is internally latched during a
write cycle.
The I/O pins will be in a high-impedance state when the outputs are disabled.
ROW/COLUMN ADDRESS SELECT: In the A/A Mux interface, the R/C pin is used
to latch the address values presented on the A[10:0] pins. The row addresses
(A10 - 0) are latched on the falling edge of R/C, and the column addresses
(A17 - A11) are latched on the rising edge of R/C.
OUTPUT ENABLE: The OE pin is used in the A/A Mux interface to control the
device’s output buffers during a read cycle.
The I/O[7:0] pins will be in high-impedance state when the OE pin is deasserted
(high).
WRITE ENABLE: The WE pin is used in the A/A Mux interface to control write
operations to the device.
READY/BUSY: The RDY/BSY pin provides the device’s ready/busy status when
using the A/A Mux interface. The RDY/BSY pin is a reflection of Status Register
bit 7, which is used to indicate whether a program or erase operation has been
completed.
Use of the RDY/BSY pin is optional, and the pin does not need to be connected.
DEVICE POWER SUPPLY: The VCC pin is used to supply the source voltage to
the device. Program and erase operations are inhibited when VCC is less than or
equal to VLKO.
Operations at invalid VCC voltages may produce spurious results and should not be
attempted.
GROUND: The ground reference for the power supply. GND should be connected
to the system ground.
NO CONNECT: NC pins have no internal connections and can be driven or left
floating. If the pins are driven, the voltage levels should comply with VIH and VIL
requirements.
RESERVED: RES pins are reserved for future device enhancements or
functionality. These pins may be left floating or may be driven. If the pins are driven,
the voltage levels should comply with VIH and VIL requirements.
These pins are used as the RDY/BSY and I/O[7:4] pins in the A/A Mux interface.
Interface
FWH/LPC A/A Mux
X
X
X
X
X
XX
XX
XX
XX
Type
Input/
Output
Input
Input
Input
Output
Power
Power
–
–
3377B–FLASH–9/03
5
5 Page 
LPC Memory
Cycles
AT49LH002
A valid LPC memory cycle begins with the host driving the FWH4/LFRAME signal low for one
or more clock cycles. While the FWH4/LFRAME signal is low, a valid START value of 0000b
must be driven on the FWH/LAD[3:0] pins. Following the START field, a CYCTYPE + DIR
(Cycle Type and Direction) field must be sent to the device to indicate the type of cycle (e.g.,
memory access, I/O access, etc.) and the direction (read or write) of the transfer. After the
CYCTYPE + DIR field has been sent, the 8-clock MADDR (Memory Address) field must be
sent to the device to provide the 32-bit starting address location of where to begin reading or
writing in the memory.
Figure 4. LPC Memory Cycle Initiation and Addressing
CLK
FWH4/LFRAME
FWH/LAD[3:0]
START
CYCTYPE
+ DIR
MADDR MADDR MADDR MADDR MADDR MADDR MADDR MADDR
START FIELD: This 1-clock field indicates the start of a cycle. It is valid on the last clock that
FWH4/LFRAME is sampled low. The start field that is used for an LPC cycle is 0000b. If the
start field that is sampled is not 0000b, then the cycle attempted is not an LPC memory cycle.
It may be a valid FWH memory cycle that the device will attempt to decode.
CYCTYPE + DIR (CYCLE TYPE AND DIRECTION) FIELD: This 1-clock field is used to indi-
cate the type of cycle and the direction of the transfer to be performed. Of the four bits placed
on the FWH/LAD[3:0] pins, bits[3:2] must be 01b to indicate that the transfer will be a memory
cycle. Values other than 01b, which may be used to specify an I/O cycle or a DMA cycle for
other components in the system, will cause the device to enter standby mode when the
FWH4/LFRAME pin is brought high and no internal operation is in progress. The
FWH/LAD[3:0] pins will also be placed in a high-impedance state.
Bit[1] is used to determine the direction of the transfer. 0 is used to indicate a read, and 1 is
used to indicate a write. Bit[0] is ignored and reserved for future use. Table 6 details the two
valid CYCTYPE + DIR fields that the device will respond to.
Table 6. Valid CYCTYPE + DIR Values
FWH/LAD[3:0] Cycle Type
010xb
LPC Memory Read
011xb
LPC Memory Write
MADDR (MEMORY ADDRESS) FIELD: This is an 8-clock field that is used to provide a 32-bit
(A31 - A0) memory address.
The AT49LH002 only decodes the last six MADDR nibbles (A23 - A0) and ignores address
bits A31 - A24 and A22 - A18. Address bit A23 is used to determine whether reads or writes to
the device will be directed to the memory array (A23 = 1) or to the register space (A23 = 0).
Addresses are transferred to the device with the most significant nibble first.
3377B–FLASH–9/03
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AT49LH004.PDF ] | |
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